Data acquisition and filtering on FPGA

[mgulin]

Dear all,

I'm having troubles designing an FPGA program for data acquisition and filtering.

I have two NI 9205 modules that are set to operate in DIFF terminal mode, i.e. there are 32 inputs that program has to read every Ts seconds. (Ts is discretization time, i.e. while loop period)

As for digital filter, I implemented a simplest filter possible with transfer function G(s)=1/(1+sT), which is in the discrete-time domain equal to y(k) = a*u(k-1) + b*y(k-1), where u is the original signal, and y is filtered signal. Coefficients a and b are equal to: a=1-exp(-Ts/T), b=exp(-Ts/T), and T is the filter time constant (usually T>5*Ts).

Here is the implementation of the main program for data acquisition and filtering:

Here is the implementation for the digital filter:

However, problem is that this program cannot fit the FPGA resources on cRIO-9114, and yes, I've tried to set the compilation criteria to area. I also tried to implement the multipliers in digital filter as LUTs and DSPs, unfortunately without any luck.

Since I don't have that much experience in FPGA programming, does anyone have any suggestions how to improve this code to fit the existing FPGA resources?

Best regards,

Marko.

[Norbert_B]

Marko,

did you set your digital filter vi to be reentrant?

Norbert

[mgulin · Accepted solution]

Hey Norbert_B,

I managed to solve the problem. First, I changed the reentrancy from Preallocated clone reentrant execution to Non-reentrant execution. Since non-reentrant VIs don't have states, I had to use the feedback node in the main VI to get u(k-1) and y(k-1). Another important thing is to select Ignore FPGA reset method in the feedback node FPGA implementation properties, since in that case the feedback node uses less resources.

Here is the new main program VI:

And here is the "filter" VI:

Thanks for the help!

Best regards,

Marko.