Demultiplexing FIFO on FPGA target

[ToeCutter]

Hi,

Is there a 'best practice' for demultiplexing multi-channel received from a single host to target FIFO within an FPGA? All the examples I can find only discuss multiplexing on the FPGA to pass multi channel data to the PC, (the 'inverse' scenario) which seems simpler.

On a related note, is it possible to read more than one sample from a FIFO per clock by using parallel FIFO read nodes?

Thanks

[nathand]

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ToeCutter wrote:

Is there a 'best practice' for demultiplexing multi-channel received from a single host to target FIFO within an FPGA? All the examples I can find only discuss multiplexing on the FPGA to pass multi channel data to the PC, (the 'inverse' scenario) which seems simpler.

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I don't quite understand the question. The critical thing is to ensure that the FPGA and host agree on the starting point so that the channels line up correctly. For example, the FPGA might signal to the host when the DMA FIFO is empty. Then, make sure you never overflow when you write to the FIFO on the host (for example, write a zero-length array, which will return the number of free elements, then write that number of elements). If you need to abort, wait until the FPGA signals that the DMA FIFO Read timed out, then do whatever you need to do to resynchronize before writing new data to the FIFO.

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ToeCutter wrote:

On a related note, is it possible to read more than one sample from a FIFO per clock by using parallel FIFO read nodes?

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No, you can't do parallel FIFO reads, at least in a single-cycle timed loop. The compiler might let you put two FIFO reads of the same FIFO in a single-cycle loop together, but the results could be unpredictable when you run it. In a non-single-cycle loop, you could do it, but you would need to enable arbitration for the FIFO which would have the effect of making the reads in series, not in parallel, and you wouldn't know which read would get which data.

[Dragis]

If your samples are small enough (4 channels x 16 bits) you can pack multiple samples within one element of a 64-bit DMA channel and then unpack those samples on the FPGA side. You can also interleave the data by pushing successive channels one after the other and then using a de-interleaving loop on the FPGA side to pop from the DMA channel and push into small single-channel FIFOs. Which way you go depends on your application.

And vote on this idea https://forums.ni.com/t5/LabVIEW-FPGA-Idea-Exchange/Allow-Cluster-and-Array-Transfer-Types-for-DMA-S... ; )

[ToeCutter]

Thanks guys- with regards to synchronisation and data packing- answers understood. My channel count dictates I will have to go with the interleaving solution and my question really was what the de-interleaving on the FPGA side should look like as a diagram, and if there is a 'textbook' preferred answer. I will effectively have a number of parallel but identical processing streams that are summed at the output end, so I guess ideally I want them all to be kicked off synchronously.

I suppose the demuxing into individual FIFO method will work if I wait for all FIFOS to have data available before I process?

[Dragis · Accepted solution]

"what the de-interleaving on the FPGA side should look like as a diagram, and if there is a 'textbook' preferred answer"

Having a separate loop that de-interleaves the data and passes the values to individual single-channel FIFOs is a very common pattern, enough so that I would say you generally want to start with that approach if each channel can be processed individually (i.e. in parallel with separate loops). 

If the channels must be processed together then it is more common to have a loop that creates a single array for each set of channel samples and then passes that array through a single FIFO to the processing loop.

In both cases, the FIFO control logic should maintain the flow correctly as long as you use the timeout or handshaking flags properly.

[ToeCutter]

Thanks again guys. If I could mark you both as providing solutions, I would.