Deploy fpga VI on a host VI

[msd11]

Hi everyone,

I have a problem which may look like simple, but I can't troubleshoot it. I have a FPGA project which someone else was working with it on a computer. Now I start using that project with the exact same hardware on a new computer and the host VI doesn't work. Attached you can see the error in the HOST VI. I did the following steps to make it work but no success so far:

1- Installing the exact version of labview (2010) along with its FPGA module and NI RIO 3.5.1 and XILING 10.1.

2- Testing the hardware and software with an example provided in the labview (http://www.ni.com/pdf/manuals/373256g.pdf). It worked perfect.

3- Use the bitfile that was generated in the previous computer to cinfigure the Host VI (Right-click the Open FPGA VI Reference function and select Configure Open FPGA VI Reference from the shortcut menu.Select the Bitfile option in the Configure Open FPGA VI Reference dialog box.Navigate to the bitfile I had to open on an FPGA target.) It didn't work and I got the same error.

4- Compile the FPGA VI and use the generated bitfile in the HOST VI in the same way as step 3. It didn't work.

5- Right-click the FPGA target in the Project Explorer window and select RIO Device Setup from the shortcut menu. The RIO Device Setup dialog box appears. Browse or type the path to the bitfile you want to download to flash memory in the Bitfile to Download path control.Click the Download Bitfile button.On the Device Settings tab, select Autoload VI on device power-up or Autoload VI on device reboot.Click the Apply Settings button. It didn't work.

Does anyone have any idea what is going on?

TIA,

MSD

[Jacobson-ni]

MSD,

What is the terminal data type of the FPGA Open VI Reference out and the terminal data type of the input to the sub VI?  Posting pictures of this may help as the data types are very large clusters if you are not configured to dynamic mode.

It is very easy to break that reference if you change anything in your project.

[msd11]

Thanks Matt for your reply.

I have attached the Host VI along with its sub VIs to this post in case you want to check it out yourself and if you have the FPGA module on your labview, you won't find any sub VI missing. All of the source and sinks data type are FPGA VI Reference and they are in match. I think there is a problem in the using FPGA VI though bitfile in the Host VI.I look forward hearing from you.

MSD

[Jacobson-ni]

Msd,

I was able to fix the broken run arrows by changing the following.

1. Double-click your Open FPGA VI reference and make sure it is linked to the correct bit file

2. Configure your hidden front panel FPGA VI Reference to reference that same bit file

3. Go into the sub-vi that is connected with the broken wire and configure the FPGA reference in and out to use the same bit file

Once everything is referencing the same bitfile, LabVIEW should be happy again.

[msd11]

Thanks Matt for your fast reply.

I think this is the solution and I reconfigure the FPGA reference in the initial X axis sub VI as you mentioned it in step 3. But I couldn't find the hidden front panel FPGA VI Reference. Can you tell me how should I find it? There is no option when I right click on the Open FPGA VI reference icon in the block diagram to show it in the front panel.

MSD

[Jacobson-ni]

Msd,

The reference I am referring to is an indicator that you created to pass information using local variables that is hidden on the front panel.

Right-click the property node that has the broken wire and Find > Terminal.  Right-click the terminal on the block diagram and Show > Indicator, your indicator will flash on the top left of your tab control.  Again, right-click the indicator to change the bitfile referenced.

[msd11]

Thanks Matt, that issue is solved.

I didn't know that your are talking about the indicator and after your last message, I found the hidden icon for FPGA VI ref and configured it.

Thanks for your help, MSD

[msd11]

Matt,

I ran into this error (Attached file). I tried to configure the "FPGA VI Ref" that the error was belong to (the section that I draw a closed red line) and gave the path of bitfile, but it didn't work. It seems that there are still some problems with Open FPGA Ref. I went through the bottom posts and tried to solve the problem but they didn't provide any viabale solution and they couldn't help. I hope you can help me out.

http://digital.ni.com/public.nsf/allkb/CB82AC9CBC6C3F2386257241007A06EF

https://forums.ni.com/t5/LabVIEW/FPGA-error-63195/td-p/1014763

http://objectmix.com/labview/339817-crio-strain-gauge-vi.html

http://forums.ni.com/t5/FieldPoint-Family/cRIO-Target-Error-63195/m-p/438052

Thanks, MSD

[Jacobson-ni]

Msd,

I would be interested to see what hapens if you

1. Delete the read/write control and just create a new one to wire up.  I've had to do this with a lot of project items before.

2. Wire directly from the FPGA Open VI Reference to the read/write control

[msd11]

Matt,

I wired directly from the FPGA Open VI Reference to the read/write control and it work.

Thanks for your help,

MSD