Determining actual Sampling Rate FPGA

[jlawley1969]

Hi, This is going to sound dumb but I wanted to confirm that my method for calculating sampling rate is correct. Because if it is then I am only getting around 4.6kS/s.

I am calculating samples as 1/looptime
and I am getting a loop time of 126uS
I have included a picture of the loop timer
and the FPGA level VI
Let me know if you need any other VIs (I doubt you will)

I am using the 9054 chassis
MOD 1 - 9381

MOD 2 - 9263
MOD 3 - 9201

For context I am working on a magnetic bearing so knowing the actual sampling rate is very important
Even more Important when I want to not use Labview's PID and develop my own.

[Bob_Schor]

Two comments:

1. There were no (as in 0) attachments.
2. "Pictures" of code (particular things as complex as FPGA code) are a PITA.  VIs are much more informative (for me, at least), but since not everyone has the "latest version", they might need to be "Save for Previous Version" specifying LabVIEW 2019 or 2021.

Bob Schor

[jlawley1969]

gotcha
not sure why they weren't attached
Ive attached 2019 compatibility
Where FPGA_Main_V7 is the actual one I care about


and dot product is one I made to just calculate --- dot product and needed to run the code

[jlawley1969]

not letting me post more than one file at a time

[jlawley1969]

still wanted to highlight the part I am using for the loop time

[GerdW]

Hi jlawley,

---

@jlawley1969 wrote:

Where FPGA_Main_V7 is the actual one I care about

---

I don't see that you "care about" that VI!

Please replace ALL LOCAL VARIABLES by wires!

There's NO NEED to put all controls into a separate loop spinning as fast as possible on your FPGA!

Suggestion to solve the overall problem:

• Place each module (aka it's IO nodes) into their own loop.
• Reading MOD1 definitely belongs in its own loop!
• Define each FXP element with the needed resolution to avoid coercion dots!
• What's the point in placing feedback nodes after reading controls/their locals???
• Avoid SGL datatype in FPGA…
• Reading MOD1 belongs in its own loop!
• What's the point of a tab container on a FPGA front panel??? A FPGA is HEADLESS…
• Attaching FPGA VIs without the LabVIEW project is mostly senseless (due to missing ALL resource definitions)…

See this:

I still missed some locals…

[jlawley1969]

Thank I appreciate the notes, still very new to Labview!

I was considering adding the whole project but I really just wanted to know if the manner in which I calculated sample time was correct.

But now that you have brought it up,  for the mods in their own loops do you mean as follows or something different ? (the rest is in its own loop)

Thanks again

[GerdW]

Hi jlawley,

---

@jlawley1969 wrote:

But now that you have brought it up,  for the mods in their own loops do you mean as follows or something different ? (the rest is in its own loop)

---

It gets better!

Now add a reasonable timing to each loop, like a 1µs (or 25 ticks for typical FPGAs) wait function…

You also might look into using specific FPGA items, like registers or memory blocks, to share data between loops. Most often there are example VIs in the example finder!