LabVIEW
Diagram Disable causes error in FPGA code
@Daklu wrote:
@User002 wrote:There seem to be a coercion dot on the FIFO, you should consider splitting up the for loop (unrolling the loop) into 4 separate filter entries for better filter presicion (if you need it?). Array based filter access are limited to 16bit FXP presicion.
Ahh... I'm so used to ignoring those in my desktop code I didn't even notice that... or understand what the implications might be. *sigh* So much to learn...
(If I could figure out what keeps causing mysterious "The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD" errors I would actually enjoy doing this.)
Learning is fun. Trivial and mundane work kills creativity. 
Fighting against the LV FPGA compiler can be a drag, though. 
Been there, done that....
Set the compiler settings to timing performance in your build configuration.
I got some seriously long compile times that ended in tears when I was clumsily bloating my FPGA code with FXP arrays.
Check so that your FPGA VI's are reentrant, otherwise you can get some really odd errors and compiler arbitration issues.
I view the FPGA as a piece of hardware I access using my (relatively clean) LV classes.
So don't bother too much about if the code looks a bit straggly and unwidely on the FPGA, compared with your "normal" LV code.
Br,
/Roger
