Digital states - high impedance state detection in FPGA vi level

[doethp]

Hello everyone, I have a question about how does the high impedance or high Z digital state look like in FPGA vi level. What I have is a PCIe 7852R multifunction card with digital IOs that are single-ended TTL.

If the digital input to the 7852R is HI or LO, I can detect the HI or LO in the vi. However, I wonder what I would see if the digital input is in high impedance mode? NI white paper says that "This state isn’t a high or low, but rather a floating or high-impedance state. It has the designation Z and is often used as an enable line." So what I would I actually see in the vi and how can I detect this?

Thanks for reading. I am looking for help.

Best,

A

[Call.Me.Wilbur]

A high impedance state isn’t a logic level that you measure like you do with logic high and low states. It’s essentially the state of a disabled line that isn’t driven to either high or low values. For example, if you probed a line that was high Z with a multimeter you could see some floating garbage value, it wouldn’t necessarily be at either of the distinct high or low levels.

The DIO pins are set to high Z when you power on the device, before you enable them as either input or output pins. However, you cannot set the pins to that state yourself as you would set them either high or low.

[doethp]

Thank you for your reply.

My experiment setup, which is currently being put together, will have the PCIe 7852R connected to a digital tri-state signal from an encoder. The input signal (coming from the encoder) to the 7852R card is at HI or LO most of the time, and only be at high impedance state when there is a mechanical/ instability error from the encoder.

You said that I will receive floating data when the DIO is at high-Z state, so can you suggest any method to implement in the VI so I can see this. What I want to do is to tell my controller VI that there is an error and it should stop taking values from the FPGA VI, which processes data from the encoder signal? (both the controller VI and the FPGA VI are in my RT system)

Looking forward to your help.

[johnsold]

I do not have any direct experience with FPGA so I cannot guarantee that the suggestion I am about to make will actually work.

To be sure that I understand the issue I will state the conditions I think you are trying to determine.

1. You are reading a signal via a digital input line and you have the specifications for its input votlage and current requirements.

2. The signal you are measuring has three possible states: Digital LO, Digital HI, and high-Z. You also have the specifications for the output drive levels for this device.

3. You know the maximum frequency of the encoder output.

My suggestion: Wire a Digital Output to the line connecting the encoder and the Digital Input through a resistor. Select the value of the resistor so that when the enocder  is actively driving the line, the input will match the encoder value. When the encoder is in the High-Z state, the value of the DO line will be read by the Input. Any time you want to check for the High-Z state, simply read the the DI line. Write the opposite value to the DO line. If the DI reading changes, then the encoder was either High-Z or just happened to change states at the same time. Changing the DO line again, especially if it can be done faster than the highest rate of the encoder, can resolve which condition occurred. The selection of the value of the resistor depends on the input and output specifications of the devices. It may not be possible to find a single value which meets all the requirements for some combinations of logic families.

Lynn

[doethp]

Lynn, would you please elaborate on your suggestion. I think I have some confusions understanding your approach. In my previous experience with the 2-state digital logic encoder, what I did was just connecting directly the encoder outputs to the digital inputs of the NI card, and then programming the input data. I am trying to visualize your sugesstion but having problems with that.

Thank you for your help.

[johnsold]

Here is a simplified diagram of my suggestion.

I am trying to look at the specifications of your DAQ device but NI's datasheet web sites are very slow at this moment.

I happen to have a CMOS databook handy so I will use the CD4001 NOR gate as an example. Other logic families will produce different results. For a 5 volt power supply the Low level input voltage is less than 1.5 V and the High level input voltage is greater than 3.5 V. The Output current is +/-0.51 mA at a voltage drop of 0.4 V at the output.

In the High-Z state of the Encoder the voltage at the Digitial Output will appear at the Digital Input because no current will be drawn through the Encoder output.  The more interesting case is when the Encoder output is active. Obviously if both the Encoder and the Digital Outupt are both Low or both High, the Digital Input will be the same as the Encoder. When the two devices are in opposite logical states is when the resistor has an effect. Suppose the Encoder is High and the Digital Output is Low. The Digital Input should remain above 3.5 V so that it reads the Encoder value.  If 0.51 mA flows through the resistor, the voltage at the Digital Output line is 0.4 V and the voltage at the Digital Input is >3.5 V, what value is required for the resistor? ~23000 ohms.

The datasheet for the 7852 finally loaded. It uses asymmetrical I/O specifications to be compatible with TTL so the calculations are a little more complicated.  You will need to calculate the values separately for the high and low cases using both minimum and maximum values for the ranges. Also use the specifications for your encoder. Then select a resistance which satisfies both cases.  It may not be possible to find a single value which will work for both. In that case two or three resistors and one or two diodes might be needed.

Lynn

[doethp]

I think I understand your suggestion. Thank you