Does FPGA front panel Boolean mechanical action matter to control actions from an RT host?

[Tinnotek]

Hi T-REX$

I just tried to figure out how the mechanical action of Boolean control in FPGA and I found this post.

I would like to know does your conclusion fits for both while loop and single cycle time loop?

Also, I found a related help article mentioned that the mechanical action differs when the FPGA VI runs on hardware versus in simulation mode. I wonder if it means as you said that all "Latch" options are equivalent to eachother, and all "Switch" options are equivalent to eachother in hardware time, but not in simulation time.

Could you help to clarify it?

Thank you

Ting

[T-REX$]

Hey Ting,

It's been a few years since I left the LabVIEW FPGA team, so my knowledge/recollection is very fuzzy...

I very rarely directly used controls/indicators inside an SCTL. I always recommended a FIFO or use a register/handshake item to transfer data to a slower/managed data->host communication loop.