FPGA 5Ms/s barrier

[ToeCutter]

Looking at the training courses, there are two FPGA courses, one for applications with <5Msample/second I/O and one for >5Ms/s.

Can someone give me an idea of what the prime differences are for developing in these two domains. I am trying to get an understanding of what knowledge is required to span the gap from <5Ms to >5Ms.

[ToeCutter]

bump... anyone?

[Eric.M · Accepted solution]

Hey ToeCutter,

In fact the 2 courses are complementary. You usually want to know how to code a "simple" FPGA application before moving on to more advanced concepts. The LV FPGA course helps you understand what a FPGA is, and how to effectively design your embedded application.

The High Throughput/FlexRIO course focuses on in-depth details of a FPGA, that allows you to have a better understanding of how a FPGA executes your code. Knowing this, you can leverage your applications in terms of speed, which is often required when you use the FlexRIO platform because of high sampling rate (AI up to 250MHz).

Also, the 5MS/s barrier is not real, because you actually learn about how to optimize speed in the first courses, with loop rate as fast as 40MHz.

If you have not gone through the courses outlines that better describe what's taught in both classes, have a look here and there !

Regards,

[ToeCutter]

Thanks very much Eric for the detailed reply!

[Dave.T]

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 Knowing this, you can leverage your applications in terms of speed, which is often required when you use the FlexRIO platform because of high sampling rate (AI up to 250MHz).

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AI up to 3 GS/s, actually!