FPGA Compile Error: Timing Violation Dialog

[RVallieu]

I just taught the LabVIEW FPGA course using LV 2010 and came across a problem with the Investigate Timing Errors dialog.

None of the items in the list were named properly and clicking on them did not locate the items on the block diagram of the code.

They were all named "block diagram object" (not sure if that was it exactly - forgot to write it down).

I am wondering if this is a LV FPGA 2010 bug?

I did report this on the instructors community as well.

[Donovan_B]

This was reported to R&D (# 248621).  It looks to be related to upgrading from 2009 and having the sequence structure in place.  I have only been able to reproduce it sometimes and not directly in 2010.  Thank you for the feedback!

[RVallieu]

Are you saying that opening existing LV 2009 FPGA code with a sequence structure in place is opened in LV 2010 may be the cause of the problem?

[Donovan_B]

I believe the code was originally written in 2009 and then upgraded.  The fact that the critical path that is to be highlighted is inside of a sequence structure AND that the code was upgraded from 2009 before being saved in 2010 looks to be the cause.  If I recreate the VI in 2010 without upgrading, I do not see this behavior.

[RVallieu]

I will keep this in mind for the class the next time I teach it.

Did you try copy paste replication into a new 2010 VI and saving and compiling or starting from scratch?

[Donovan_B]

I didn't try copy/paste, I just redid it from scratch.

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[EvenDeejay]

Please use the Job Opening and post a new thread, hanyang. Spamming random and sometimes old/dead threads will not help you much!

Since I'm answering the same on all your post about this topic, it looks like I'm also spamming

So i'll stop now. Please post in the Job Openings instead.

[tamirsh]

It`s like my problem. I upgrade my  LabVIEW 9  to  LabVIEW 10 sp1 (because start using the CRIO-9075 instead the CRIO-9074).

Than, I try to compile again the FPGA VIs in LV10 (as the NI people told me to do), and it FAIL with the "Timing Violation Error".

What do I have to do?

When I opened the Error reasone, it send me to an ADD command into a loop that in a Structure like in the attached file.

What can I do with it?

[REDS]

Hello tamirsh,

Thanks for posting in the Discussion Forums! I see that your code has quite a lot of logic on the while loop. Following the recommendations on the Fixing Timing Violations (FPGA Module) help file, you can reduce the long combinatorial paths by using pipelining or Using Single-Cycle Timed Loops to Optimize FPGA VIs (FPGA Module). I hope this helps.