回复： FPGA DMA FIFO

[jamse]

Hi bro !

The FPGA of the lower computer reads a large amount of data sent by the host.With hundreds of thousands of data to go through, the lower machine can't use too many for loops，

I don't know what to do

[jamse]

The procedure is as follows

[ZYOng · Accepted solution]

How many data points are you streaming from the host per iteration? How many data points are you streaming per second?

What is the model of the R Series device, chassis and controller? Are those devices PXI or PXIe? Which slot is your 7821R slotted?

[jamse]

Mine is NI-PCIe7821R device, the chassis is a common industrial computer box, currently under test, PCIe 4 slot, I need four channels, each channel to read more than one hundred thousand one-dimensional data sent from the host, are U32 bits, the faster the better.

[jamse]

Mine is NI-PCIe7821R device, the chassis is a common industrial computer box, currently under test, PCIe 4 slot, I need four channels, each channel to read more than one hundred thousand one-dimensional data sent from the host, are U32 bits, the faster the better

[ZYOng · Accepted solution]

Assuming that you are trying to stream 4 channels of 100k U32 data points per second. The data rate is 100k * 4 bytes * 4 channels = 16MB/s, which is way below the 250MB/s per lane throughput of PCIe Gen1.

What is the issue you are seeing with your LVFPGA coding? Is the FIFO timed out? Can you try to Measure Real FPGA Loop Time?

[jamse]

I want to try to put the data transmitted from the host computer into an array of FPGA programs, the data stream can be to, but can not form an array. for example, I use for loop 100 this or shift register these functions, can only store 100 data into an array, for loop a little larger or use shift register through the array is very large, the FPGA program can not be downloaded to the FPGA board.

PLAN A:

         Try to store the four channels in FPGA 100,000 data into four arrays, four channels data volume is very large, and FPGA also includes to process these data programs. I'm afraid FPGA doesn't have so many resources.

PLAN B:

          At present, After reading 100,000 pieces of data in the EXCEL table in the host computer, I grouped them and sent them to the FPGA board with FIFO in turn. Then want to do a cache pool buffer data in the FPGA program. You use one set of data, the next set of data comes along. Similar to the host queue function. But I do not know how to implement it in the FPGA program, and the upper computer with FIFO, and the next machine FIFO timing grasp is not good.

       If you have a solution for the two solutions or you have a new solution, please help me, I would be very grateful.

[ZYOng]

The first issue I am seeing here is the error on the dynamic array. Unlike software, FPGA cannot allocate array size at runtime. You cannot use the indexed output tunnel in FPGA. Use Replace Array Subset with an initialized array instead.

Let's worry about the resource utilization issue later, after you have resolved the dynamic array size. The NI LabVIEW High-Performance FPGA Developer's Guide provides the best practice and optimization that you can do.

Besides, you should stop marking all of my replies as Solution. They are not the actual solution to your question. This is confusing to others. You can just click the little star at the bottom left of the reply to give a kudo instead.