FPGA DRAM syncing with Host VI

[Layke]

So I am trying to write a simple FPGA VI / Windows Host VI that let's a user write and read values from a FlexRIO's DRAM, and while my FPGA VI works just fine, I am having serious synchronization issues when trying to use the host to control the FPGA VI.  Is there a good example of reading and writing to DRAM from a host anywhere or a similar project someone has done.  Any help in regards on how to properly synchronize this type of application would be greatly appreciated as well.  Thanks in advance!

[dan_u]

The host can't access the DRAM on the FPGA directly. You will have to use DMA FIFOs (or FP controls) to exchange data between host and FPGA.

Probably you're confused about the term DMA (direct memory access)? DMA is about the memory on the host (the PXI controller), not the DRAM on the FPGA.

There are examples for both FPGA DRAM (accessible from the FPGA only) and for DMA (accessible from both FPGA and host via DMA FIFOs).

[Layke]

No, I'm using FPGA Interfaces to execute my controls on the FPGA VI, but specifically I am having trouble syncing the write, read request, and read retrieve functions within the FPGA VI in order to make sure that when a "Read/Write" switch is enabled on the device and an "Execute Operation" is triggered, the FPGA VI performs the required action and the Host VI sends and receives the data to be written and read without causing synchronization chaos.  Is that a little more clear?

[dan_u]

Still I would suggest using DMA FIFOs between host and FPGA. With DMA you don't have synchronization issues since it's queued.

Of course it's possible using controls, but speed will be quite limited since you need to be more careful about synchronization.

A FIFO element (host -> target) could contain the command (read/write), the address (if that is controlled from the host), and the data (for a write command).

The target -> host FIFO would return the data from the read requests.

On the FPGA you could implement a state machine, if there is an element in the FIFO evaluate the command (read/write) and run through the necessary states to read (read request/read and write to FIFO) or write.

[Layke]

I hear ya, and trust me, I would use FIFOs, but the exercise it one to learn the underlying principles between synchronization, not the most "efficient" method.  You build with bricks before beams.