10-18-2024 03:04 AM
Dear LV enthusiasts,
Is there any way to determine how many ticks are needed for the execution of a for-loop or a VI? The code isn't running as fast as required, and I would like to identify the bottleneck. Maybe some simulation?
Thank you in advance!
10-18-2024 03:05 AM
10-18-2024 03:53 AM
No answer to your question, but...
Put time critical code in a single cycle timed loop.
This ensures it takes 1 tick... It won't compile if it doesn't fit.
10-18-2024 06:19 PM
Use the LabVIEW FPGA Desktop Execution Node to get accurate timing in simulation mode.
10-21-2024 03:23 AM
@ZYOng wrote:
Use the LabVIEW FPGA Desktop Execution Node to get accurate timing in simulation mode.
First time I heart about that...
I'll still stick to the SCTL whenever I can, so I hope I remember this tool if I ever need it.