FPGA FIFO i read the old FIFO in RT

[agibello]

Hello there,

Im trying to read a FIFO but i cant see the 5 Temp FIFO,

I think im missing something but i dont know what.

When I ran the program RT is reading the 'old' FIFO but I compile with the new variable, so i think the trick could be there.

Thank you in advance

[Bob_Schor]

We have to be able to see and study your code, which means we need the code, not a picture of part of the code (LabVIEW code is three-dimensional, and a 2-D picture just isn't adequate!).

Please attach the FPGA code as a VI.  You should also know that you probably want long-time LabVIEW users (who are more likely to be "experts") to be able to open and read your VI, so you should "Save for Previous Version" and specify LabVIEW 2019 or 2021 to reach these users.

Bob Schor

[agibello]

Thanks, Im sorry i thoutgh it was enough for my issue.

Attached the VI of the FPG and where im trying to read the FIFO.

I cant see the fifo thats why i was sending the image

[raphschru]

Hi agibello,

If you don't see the FPGA DMA FIFOs or Controls you expect on the RT side, depending on how you open your FPGA VI reference, it can mean that you are either:

1. Referencing an older bitfile (compiled FPGA VI, with .lvbitx extension);

2. Pointing to the wrong FPGA VI / Build Specification;

3. Or that you have not updated your dynamic FPGA reference type.

Go to the part of your RT code where the FPGA VI reference is opened.

I assume you will have an "Open FPGA VI Reference" node (cases 1. or 2.):

By right-clicking it > Configure Open FPGA VI Reference... , make sure it references the correct bitfile, VI or Build Specification.

If you reference a bitfile, the RT side will only update when the bitfile is recompiled.

If you reference an FPGA VI or Build Specification, the RT side will update directly while you make changes to the FPGA VI.

Regards,

Raphaël.

EDIT: The RT VI you attached does NOT contain the opening of the FPGA VI reference. It is done somewhere else in your RT code.

[agibello]

Hey Rapha,

Thank you for your answer,

You are right i have in another VI. I made what you suggested and now I see the FIFO i want. 

but look what happens when i change the reference, I dont know whats happening there

I dont really understand what's happening and then affects to the RT main. 

The software was done and im doing modifications.

Let me know if you need a more specific files o explanation.

Thank you again for your help.

[Intaris]

Under the assumption that your Bitfile is correct:

There are issues with type propagation of FPGA refnums on RT systems.

We regularly run into the situation where just re-linking the bitfile does not propagate the changes in Refnum properly.

If you wire to a structure or shift register, disconnect it from your source and then re-connect. That might help the new FPGA reference propagate properly.

[raphschru · Accepted solution]

So, as I can see, you have an "Open FPGA VI Reference" node that references a bitfile, configured in dynamic mode.

You have a broken wire because the reference input/output of your SubVIs are linked to a type definition called "FPGA VI Reference Out.ctl" that mismatches the type given by the "Open FPGA VI Reference" node.

2 solutions:

1. Update your type definition manually:

Right-click one of the FPGA refnum controls > Open Type Def.:

Right-click the reference control in the type def > Configure FPGA VI Reference...:

Import configuration from either your FPGA VI or your bitfile > press OK:

2. Alternatively, if you prefer your type definition to update automatically each time you update either your bitfile, FPGA VI or FPGA Build Specification, you can make your type definition auto-update based on the "Open FPGA VI Reference" node configuration:

Right-click on the "Open FPGA VI Reference" node > Configure Open FPGA VI Reference...:

Uncheck "Dynamic mode", check "Bind FPGA host reference to type definition", choose your type definition (in your case "FPGA VI Reference Out.ctl":

The second technique might have impact in case some of your code requires a "Dynamic" FPGA VI Reference type. This type of reference allows more abstract implementations to fit with different FPGA VIs (but I doubt it is your case though...).

In both cases, your type definition will be updated, unbreaking the wires to the inputs/outputs (that are linked to the type def) of your subVIs.

Regards,

Raphaël.