FPGA Filter Utilization

[jlgeris]

I'm currently using a succession of filters in an application of mine. My question is that I've noticed performance benefits, via resource saving, implementing the multiple filters in a For-Loop. The caveat is that for my Butterworth filter, I cannot configure it for multiple channels because I need the filter configured for an Order of 4. For the second filter, it is acceptable to use the multiple channel configuration. Please see my examples in the attached Block Diagram. It appears that the 1st case is more efficient regarding resource usage on the FPGA. Would anyone see a reason why both cases would produce different results? Additionally, would Feedback Nodes increase efficiency? Thanks!

[jlgeris]

I seem to not be able to upload the image as an attachment. Here's a link. http://i.imgur.com/sqPoy.png

[JLewis · Accepted solution]

The first method is treating the 4 AIs as a single channel, so it is not doing what you want. The second method is correct, but costs more since it has to instantiate 4 independent filters.

One option would be to cascade 2nd order multichannel filters to make a 4th order. Use the single-channel 4th order "Butterworth Coefficients" VI from the FPGA Interface>>Scaling palette to get the 6 coefficients you need. Pass 3 of those coefficients into each 2nd order stage. I haven't tried this myself, but can help if you run into problems.

I don't see any benefit to adding feedback nodes, but am not sure what you have in mind there.

[srm@viewpointusa.com]

LabVIEW 2010 allow you to configure the butterworth for multiple channels so the first diagram would work if you make that change.

[jlgeris]

Thank you. I will see if I can implement your recommendation as well.