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FPGA Memory block

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Hi jamse,

 

what is your question?

Which FPGA target are we talking about?

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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BRAM is typically organised in 36kb blocks (kilobit, not Kilobyte) and your target will tell you how many of these instances you have available.

 

Expanding beyond the supported 1 to 36-bit width read/write interface will cost more BRAM as each BRAM can only handle 36 bits, more will be handled in parallel.

 

Increasing the depth will scale also of course.

 

So 24 bit x 2,000 elements will require 2x BRAM entity. 24 bit x 20,000 will require 13.

 

1 bit x 2,000 requires 1 BRAM. 1 bit x 20,000 still requires only 1 BRAM as it is less than 36kb.

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NI -PCIe7821R 

I want to ask the memory can he store so much data?

Nearly a hundred thousand.

The upper computer reads the data of the excel table,It is sent to memory via FIFO

As shown in the figure, each column of data is stored in a separate memory, and each column contains about a hundred thousand such data

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Hi jamse,

 


@jamse wrote:

NI -PCIe7821R 

I want to ask the memory can he store so much data?

Nearly a hundred thousand.


Read the specs! (paragraph on "Reconfigurable FPGA")

It offers 11,700 kbits of BlockRAM: use the information given by Intaris to compare with your requirements…

 

Spoiler
Simple math: 2 channels * 100k elements/channel * 8bits/element = 1600 kbits.
When using 16bit data you need 3200 kbits…

Why do you want to store several "tables" of >=100k elements in the FPGA?

 

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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A FIFO and BRAM are not the same thing, is the FIFO on FPGA, from host to FPGA, from FPGA to host?

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  • Thank you, brother.

The element type I'm using is U32, 800,000 elements in four stores, 200,000 elements in each store. I calculated that 32*800k/32=25000kbits is beyond the manual. But the download was successful.

 

My purpose is to let the FPGA output signal according to my time and data. Because then I can plan the path of the laser.

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Hi jamse,

 


@jamse wrote:

The element type I'm using is U32, 800,000 elements in four stores, 200,000 elements in each store. I calculated that 32*800k/32=25000kbits is beyond the manual. But the download was successful.


Do you really need U32 values?

Do you really need 200k elements per signal?

(4 channels * 32bit/channel * 200k = 25600 kbits)

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Thank you for your answer.

Yes, the host sends data to FPGA using FIFO, saves the data to the memory, and then I use the data according to the address. What is the maximum number of elements of type u32 that can be stored in pcie7821's memory? Let's see, 11,700 times 32 is 374,400 elements, right? brother

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Hi jamse,

 


@jamse wrote:

What is the maximum number of elements of type u32 that can be stored in pcie7821's memory? Let's see, 11,700 times 32 is 374,400 elements, right?


It seems simple math is not your strength:

11,700 kbits / 32 bits/element = 11,700,000 / 32 elements = 365,625 elements

 

(When the BRAM is organized in 36 bit entities then this may reduce to 325,000 elements as each U32 element may occupy a 36 bit entity…)

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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