Hello all!
I'm using cRIO 9074 and its FPGA for data acquisition of a DC/DC converter. Since switching frequency of the converter is 30 kHz (~ 33.33 us), I need a microsecond domain. Because of that I use FPGA instead of RT, along with NI I/O modules which can achieve speed of 100 kS/s (i.e., period of 10 us). In order to be able to see what is actually happening in the converter, data acquisition frequency has to be greater than its switching frequency, so I tried to set 10 us period for my FPGA VI, since this is the refresh rate of I/O modules. However, it seems that the data are recorded with 37 us (constant period between two samples in whole data set) rather than with 10 us. If I set e.g. 50 us acquisition period, cRIO will record data with 50 us - in fact, if I set anything greater than 37 us, cRIO will respect that period!
My question: is this kind of behaviour due to the how I wrote the FPGA VI, or this 37 us period is just an inherent limitation of FPGA on cRIO 9074? Since I use only I/O modules and DMA FIFO for communication with a PC, I don't know what could be the bottleneck here.
Colleague of mine also experienced a similar issue, but in his case it is 15 us period (his FPGA VI just can't go below this). Worth noting, he uses a different cRIO, but unfortunately I'm not quite sure which one.
Thanks!!
Best regards,
Marko.
