FPGA: Using Xilinx FIFO generator FIFO between two SCTLs

[michaeljoseph]

Hello,

--- Summary:

I am trying to use a Xilinx FIFO generated FIFO to transfer data between two SCTLs (each in a different clock domain). However, when I finish generating the IP, labview gives just one VI for the FIFO that contains both the read and write interface (attached picture). In other words, I can't physically place the read interface in one SCTL and the write interface in the other SCTL in the block diagram. 

Am I missing something, or is my only solution in this case to try to instantiate the FIFO myself using custom CLIP?

--- Application:

I want to use the FIFO to implement aspect ratio adjustment for some data processing (ex: write 56 bits at clk rate A, read 28 bits at clk rate A*2). In the past I have used my own VIs in combination with LabVIEW-generated FIFOs to implement aspect ratio adjustment, so it is not a major setback if CLIP is the only solution. I just have no experience creating custom CLIP. 

Thank you,

Michael

[Daniel.Parrott]

Hi Michael,

To be honest I'm not too familiar with using the xilinx FIFO Generator, so I'll have to play around with it a bit. I feel like there should be a way to read/write to the same FIFO in different spots. Unfortuntately there's not much documentation on the xilinx IP functions in LabVIEW. 

Another question though. Why wouldn't a regular Target-Scoped LabVIEW generated FIFO work for you in this application? I guess if you're mentioning custom CLIPs are you working with an sbRIO? I think I'm a bit confused as to why you'd have to create a custom CLIP for this.

[michaeljoseph]

Hi Da_Parrot,

Thanks for your reply.

I feel like there should be a way to read/write to the same FIFO in different spots

Yes I am hoping someone has ran into this situation before. It seems like if we can't read/write in different spots it would limit the use of the Xilinx FIFO generated FIFOs to the scope of one SCTL. This makes me think that I am missing something.

Another question though. Why wouldn't a regular Target-Scoped LabVIEW generated FIFO work for you in this application? I guess if you're mentioning custom CLIPs are you working with an sbRIO? I think I'm a bit confused as to why you'd have to create a custom CLIP for this.

My plan was to use the FIFO for aspect ratio control as it moved data between clock domains. For example, I have some data acquisition code that operates at 4 points per clock cycle at clock rate A, then I want to do my processing at 2 points per clock cycle at clock rate 2*A. So I would put the data into the FIFO in chunks of 4 and read it out in chunks of 2 like this: 

data acquisition - clk rate A:

4 data chunks => FIFO

processing - clk rate 2*A

FIFO => 2 data chunks

From what I understand, the LabVIEW generated FIFOs do not have any aspect ratio control similar to the Xilinx FIFO generator. But maybe I have missed some options? Assuming there is no option, I figured that custom CLIP was the only alternative. 

In the past I have used my own logic to perform aspect ratio control around LabVIEW generated FIFOs (see below). But I suspect that my logic is not as efficient as whatever logic Xilinx has built-in to their FIFO generator. That's why I am trying to perform aspect ratio adjustment in the Xilinx generated FIFO.

data acquisition - clk rate A:

4 data chunks => FIFO

processing - clk rate 2*A

FIFO => 4 data chunks [only read FIFO every other clk, send 2 data chunks downstream every clk]

Thanks,

Michael

[Daniel.Parrott]

Hi Michael,

The only way I could figure you'll be able to use the Xilinx Generate FIFO IP between two SCTLs is putting it in a subVI and calling that in the two SCTLs. 

If you check out page 25 of this document it shows an example of this, however it's only showing that it's used in one SCTL. https://decibel.ni.com/content/docs/DOC-11842

Also it doesn't look like there's a way to control the aspect ratio with LabVIEW generated FIFO's. Using the LabVIEW FIFO you'd have to write/read from the FIFO only once per SCTL iteration. 

I'd also considering checking out the LabVIEW FPGA High Performance Guide: http://download.ni.com/pub/gdc/tut/labview_high-perf_fpga_v1.1.pdf. I went through it to see if anything like you're trying to do was referenced in it and didn't find much, but it's definitely worth bookmarking for the future.

[michaeljoseph]

Hi Da_Parrot,

Thanks for your response.

---

The only way I could figure you'll be able to use the Xilinx Generate FIFO IP between two SCTLs is putting it in a subVI and calling that in the two SCTLs.  

I'm not sure if I follow. I don't think it would work because placing the subVI in two SCTLs would instantiate two different FIFOs. This is because the subVI is operating in the 'preallocated clone reentrant execution' mode when it is in a SCTL. From what I understand, this is the only option for reentrancy in a SCTL. 

I did some searching and it looks like subVIs cannot operate in either of the reentrant modes when they are in SCTLs: http://digital.ni.com/public.nsf/allkb/57475363E7BC8D9D86257117005C291E?OpenDocument. So what I expect would happen is one FIFO would be written to but not read from, and the other FIFO would be read from but not written to.

---

Ultimately I ended up implementing the FIFO using custom CLIP. 

The main hurdle that I encountered, in case this may help anyone in the future, was figuring out that I had to use the version of Xilinx ISE installed with LabVIEW FPGA. I needed Virtex-5 support for my FPGA, and Virtex-5 is not supported with the free version of ISE, webpack. I had no idea that it was accessible from outside of LabVIEW. Here is the path (32-bit version) on my machine: "H:\NIFPGA\programs\Xilinx14_7\ISE\bin\nt\ise.exe". 

Once I generated the FIFO in Xilinx ISE, I used the CLIP wizard (http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_clip_using_wizard/) to add the Xilinx coregen FIFO files to my LabVIEW FPGA project.

So I guess we've answered my question? Currently the only way to include a FIFO with an asymmetric aspect ratio is with custom CLIP.

Thanks!

[Daniel.Parrott]

Hi Michael,

Thanks for the update! And thanks a lot for including the problems you ran into during the process. I'm glad you got it all working using the custom CLIP.