FPGA Write/Read DMA FIFO for multiple channels - FOR loop vs multiple FIFOs

[abvenk]

Hi all,

I'm using LabVIEW 2014 with FPGA module. Hardware is NI 9146. I have multiple Analog Input channels of which I need to write data to DMA FIFO in the FPGA VI, and then read from DMA FIFO in the host VI.

What is the "correct" method to write/read:

1. Build an array with the analog inputs, use FOR loop to Write, and use Decimate Array to segregate the channels at Read.

2. Use multiple FIFO's to write and corresponding FIFO's to read.

I'm keeping track of elements remaining, to make sure there is no overflow. 

I've tried both methods, and I get different end results. I'm not sure which method guarantees data integrity.

Can someone throw some light on this please?

Thanks.

[Intaris]

You have made tests, get different results and are not sure which one guarantees data integrity?

I think you need to think more about what you are doing so that you can immediately reject one or both approaches if the received data does not correspond to what you were expecting.

In other words, build a test where your starting point is known and then try to pass this via DMA and check to see if the end result is correct or not.  What is "right" depends a lot on what exactly you are trying to do.

PS One thing I will say, if the data width of your individual dat apoints is 32 bits or less, place them both in a single 64-bit value and use a single 64-bit DMA instead of trying to synchronise 2 DMAs.

[abvenk]

Yes, what you said occurred to me right after I posted this question. So I'm in the process of testing with known signals.

But I still want to know if there is an "official" recommended method for multiple channels. 

[Kevin.MN]

No official recommendation that I could find for your specific implementation. The closest we get is recommending DMA FIFOs for FPGA/Host data transfer.

Whichever route successfully reports your known input would be "recommended" in this case.

[abvenk]

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@Kevin.MN wrote:

No official recommendation that I could find for your specific implementation. The closest we get is recommending DMA FIFOs for FPGA/Host data transfer.

Whichever route successfully reports your known input would be "recommended" in this case.

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Thanks for your reply. 

I also have a related question about the behavior of the 'FFT Express VI' on the FPGA side and the 'FFT-to-Spectrum' VI on the host side. Is there any difference in those functions between LV2014 and LV2016?

[Kevin.MN]

Looks like you've done the proper thing and moved the follow-up question to a new thread. I'll check in on the other thread, and ensure that it doesn't die.

[abvenk]

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@Kevin.MN wrote:

Looks like you've done the proper thing and moved the follow-up question to a new thread. I'll check in on the other thread, and ensure that it doesn't die.

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Ok Thanks.