FPGA and NI 9144

[cuaerospace]

Hi,

I am having trouble figuring out how to access FPGA I/O channels on the EtherCAT NI 9144.

I am using an NI 9214 card in the 9144 extended chassis. I would like to access the FPGA I/O channel values FROM the host VI. 

All I want the host VI to do is access those channel values and run them through our custom calibration code. Must I use FIFO? If so, can someone advise as to how I use FIFO.

Or, is there an easier way? I tried dragging the channels from an FPGA instance I created on the 9144 to an FPGA instance that is actually written on the cRIO I am using.

Thanks!

[DirkW]

The ECAT LabVIEW help should explain the FPGA use case. Look under Start>>All Programs>> National Instruments>> NI-Industrial Communications for EtherCAT>> help file

The FPGA use case is slightly different from the normal Local chassis use case. You do mot have DMA or host interface and you do not have debugging.

The only method of communication/data exchange between 9144 and your controller is a user defined variable. (UDV). If you right click your 9144 in project and choose NEW>> User defined variable you can create one for either 9144 FPGA to RT Controller or the other way around. It has only single data types no arrays. ;-(

There are several examples like the synchronization one that show how to use it.

Hope that helps.

DirkW

[cuaerospace]

Hello, thank you for your reply.

I did use the user defined variable option but now I am having errors creating the bitfile when I compile the FPGA VI on the 9144. 

The error has to do with xilinx, I'm not sure what this means. Here is a snippet:

LabVIEW FPGA: The compilation failed due to a xilinx error.

Details:
ERROR:HDLCompiler:1233 - "\NIFPGA\jobs\B05c98o_XI64xG6\NiFpgaDualPortRam_Inferred.vhd" Line 110: Array size is larger than 2**28
ERROR:HDLCompiler:410 - "\NIFPGA\jobs\B05c98o_XI64xG6\NiFpgaDualPortRam_Inferred.vhd" Line 110: Expression has 0 elements ; expected 536870912

I've created an FPGA target on the slave device and I have the FPGA VI running a single while loop that uses a sequence structure that writes individual I/O channels from my thermocouple card to the FIFO buffer. The following frames in the sequence structure write to user defined variables, separately. I use small wait times in each window to allow the data transfer to take place properly.

I then have a VI on the host which processes the user defined variables. I have the variables defined in the right 'direction' - from fpga to host. 

Is this a sound approach?

Also, does it matter if my host vi is placed under my RT cRio or my computer in the project explorer.

Thank you!