FPGA code stops when RT code stops

[WNM]

I have developed some FPGA code to manage a piece of hardware. It's setup to read some default front-panel control configuration values and then sit there endlessly responding to signal inputs and producing signal outputs.  The FPGA bitfile is written to flash memory so the FPGA loads and starts running almost immediately. So far all is good. 

Next I layered onto the system (cRIO-9075) some RT code which opens an FPGA reference to the FPGA front panel and allows me to monitor a few indicators and change the configuration settings and cause the changed configuration settings to be used by the FPGA.   So far this seems to work too when I run the RT code interactively (eventually there will be an interface to a host system).

The problem occurs when the RT code is commanded to stop. Stopping the RT code also causes the FPGA code to stop and I don't want the FPGA code to stop. The RT code does not make any calls to command that the FPGA code abort execution. When the RT code is stopped, the only thing it does with regard to the link to the FPGA is to close the FPGA VI reference that was opened when the RT code was started.

What do I need to be doing to cause the FPGA code to continue to run as the RT code is started and stopped?

[WNM · Accepted solution]

I'll have to wait until I get back to the office tomorrow to test this but I think this link has the answer to my problem.

http://lavag.org/topic/16412-confusion-regarding-fpga-deployment/#entry100294

It says: "the Close FPGA reference VI. If you right click you have an option to close or by default close and reset. This means the FPGA VI is reset (read aborted in standard LV speak) when we close the reference."

[nathand]

From the help: "By default, the Close FPGA VI Reference function closes the reference to the FPGA VI and resets the FPGA VI. To configure this function only to close the reference, right-click the function and select Close from the shortcut menu."