FPGA error - Internally pipelined object not connected to enough feedback nodes

[charansai]

Hello everyone,

I am trying to implement LMS on FPGA module of myRIO 1900. I could not understand fully the following error.

''Memory Read : Internally pipelined object not connected to enough feedback nodes''

Details:

''The selected object has an embedded shift register that makes the output on a particular loop iteration correspond to the inputs from the previous iteration.

Wire the outputs for the object directly to the minimum number of Feedback Nodes or uninitialized shift registers. You cannot wire the outputs to another object.''

I just tried to access values from two memories and add them. The address values for the two memories are same but both memories are different. I tried to implement this on SCTL, it is not working but on normal while loop, it is working.

Help me understand the error.

Thank You.

[Jacobson-ni · Accepted solution]

Posting a snippet of your code would help us be more confident but I think you are running into the error described in the second note of this help documentation.

http://zone.ni.com/reference/en-XX/help/371599L-01/lvfpgaconcepts/fpga_memory_items/

Using the default memory item settings you have to attach a feedback node with a x2 latency on the read output to use it inside of a single cycle timed loop.

[charansai]

@Jacobson Thank you ! That was the problem.

But I still coudn't understand the theory behind it! Can you please tell me , what are cycles of latency ?

[Jacobson-ni]

If you have a snippet of your code that you can post I would probably be able to get a more definite answer but my understanding right now is that the read takes a certain amount of cycles to complete and retrieve the correct data. In the help document's example this would mean that the data output would not be that of the requested adress until two cycles later.

Page 79 of the High Performance FPGA Developer's Guide discusses memory items with a bit more depth and mentions this.

http://download.ni.com/pub/gdc/tut/labview_high-perf_fpga_v1.1.pdf

[tobiy]

Is it only me or is the mandatory feedback node after the Data output very confusing ?

I mean the report even says that the read method has an "embedded feedback node" and that its output corresponds to previous requests.. So in my logic, adding any more feedback nodes would delay the output more than the natural read latency.

This practise is also in contrast with basically every other memory interface present in Labview FPGA. In other interfaces such Fifos and Handshakes, a valid output is immediately useful, but it arrives only after some latency signaled by a valid flag.

[gregoryng]

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Is it only me or is the mandatory feedback node after the Data output very confusing ?

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I wanted to chime in here and say that it's not just you.  The instructions are clear, but the reasoning seems counterintuitive to me for the reason you explained.

Certainly the outcome than what I did intuitively  which is to add pipeline delays to all my other signals.

If anyone could explain the intuition, that would be great.

[Hassan4488]

Used LUT instead of BLOCK Memory. 

[Intaris]

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@Hassan4488 wrote:

Used LUT instead of BLOCK Memory. 

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Not neccessarily a great choice IMHO.

The shift registers you need to add after a BRAM read will be pulled into the internal registers during compilation by Xilinx.

I can confirm that if you add two SRs after a BRAM read, the latency is indeed 2. It does not add two to the internal register.

I will, however, add that the implementation is quite unclear and feels cumbersome if you start educating yourself. I think it's just a corner case where the LV definition and the Xilinx implementation just differ slightly.