FPGA error

[jeromelei]

Hi

I am now doing a work to send data from the computer to the sbRIO and get the digital output using oscilloscope. I used Host to Target FIFO and a handshake like system to avoid the overflow and underflow. The program seems fine when i run it on the Development computer with simulated I/O. However, when i try to compile it and run it on the real FPGA target, it shows several errors.

The first is compilation shown in the first screenshot.

I ignore this warning and continue to run. BUt it shows the secnd one.

And even if there is no error showing, it just doesnt work between the host vi and the FPGA vi.

Hope I explained clearly and someone can help a bit, Thank you!

[crossrulz]

First thing I would do is see if this patch works: LabVIEW FPGA Module 2013 SP1 Xilinx Tools 14.4 f1

[jeromelei]

Thank you for replying.

But I would like to say that My FPGA board is sbRIO-9631, which is xilinx spartan-3. What's more, my system is 64-bit.So is it ok for me to use this patch?

[crossrulz]

Ok, after a little poling around, I found this white paper:Which Version of the Xilinx Compile Tools Do I Need to Compile My LabVIEW FPGA Code?

So your sbRIO-9631 needs the Xilinx Tools 10.1.  This compiler is part of the Additional FPGA Toolset disc.  Make sure you have that installed.

Managed to find the download here if you don't have the disk:NI LabVIEW 2013 FPGA Module Xilinx Tools 10.1

[jeromelei]

Thank you for replying.

I found this in my compile worker. (see attachment)   Is this ok?

[crossrulz]

That looks like it should be ok.

[jeromelei]

Thank you for replying.

I have solved the compilation warning problem.

However, the second one, run of source and close a session and retry the operation problem is still there. May I ask how should  solve this problem? Thank you!

[Spex]

Regarding the second error, I wouldl recommend attempting to compile a simple LabVIEW FPGA VI to determine if the error is related to the compiler, OS, or other infrastructure.  If a simple VI compiles successfully, then it will inidcate that the source of the error is likely something in your LabVIEW FPGA VI.

Regards,

[jeromelei]

Thank you for replying.

I have already tried a simple code. It is compiled and run successfully. So i really dont know why.

I am now trying this way: repairing the NI-RIO dirvers and try again. If it still couldnt work, then i really dont know what i can do now.

[Spex]

If a simple VI compiles successfully, then it is unlikely to be a problem with installed SW.  More likely there is something wrong with how something is configured in your VI.

The most straightforward method for finding the problem is to cut things out of your design and see when it compiles.   

The things that I would suspect may be causing the error are things like memory, FIFOs or DMA FIFOs. Are you using these features? If so, how large are the buffers assigned to those resources?  There are limitations in the amount of memory available to the FPGA, which are documented in the user manual for your target.  If you assign bufferes too large, this may be the way the compiler fails.

Regards,