07-14-2006 11:00 AM
07-17-2006 10:24 AM
Hello Emmanuelle,
You will have different function palettes available to you depending on what hardware you are currently targetting. If you are developing the VI that will be compiled to VHDL and run on the FPGA itself, the FPGA IO Node is all that you need to acquire data from the digital lines. You can then use FIFO buffers to send the data to your Real-Time or Windows VI, which will use the "Open FPGA VI Reference" function in conjunction with FIFO reads to reference the appropriate data items. There are some very good examples of this included with the LabVIEW FPGA module that will demonstrate the process. Let me know if you need more information!