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FPGA

Who will use the NI PCE7821 R data acquisition board, my need is to read from the host host program, read the data to the FPGA use.

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Message 1 of 13
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What's your exact question?

If you want some guidance to get started, refer to the shipping examples at Help >> Find Examples... >> Hardware Input and Output >> R Series

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Control Lead | Intelline Inc
Message 2 of 13
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1.The real question is how does the FPGA accurately receive and use the hundreds of thousands of data sent from the upper computer?

2.I use the FIFO transmission of the upper computer, the next computer also uses the FIFO reception, how to ensure the integrity of the data?

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Message 3 of 13
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ZYOng

God help me look

:Will data loss occur when the fpga receives data from the host in this way?

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Message 4 of 13
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See How DMA Transfers Work (FPGA Module)

 

Your code looks good. As long as you are configuring the correct buffer size and using the correct write rate so that fifo overflow or underflow does not occur, there will be no data loss.

You can use the Timeout? output to monitor if fifo overflow or underflow happens.

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Control Lead | Intelline Inc
Message 5 of 13
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Thank you, God

I'm sorry to trouble you again,When I run the fpga, I get a timeout,Can you help me to see how to configure my PC/host program.Such as buttfer and rate.

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Message 6 of 13
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Brother help me look

 

Why is this possible in my simulation and not in reality?

 

The video is a simulation and real.

 

I want the effect to be simulated

 

1f93dfa76ddcd115faafe4afc17867c.png

174549ab4e2b8091a75a085b7103929.png

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Message 7 of 13
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Memory DRAM  ,  I use PCIe 7821R hardware.

  • Can this memory read data at intervals?

  • I actually tested it, and the interval read was unstable.

    • Is it because Memory can't read at intervals?

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Message 8 of 13
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Hi jamse,

 


@jamse wrote:

Memory DRAM  ,  I use PCIe 7821R hardware.

  • Can this memory read data at intervals?

  • I actually tested it, and the interval read was unstable.

    • Is it because Memory can't read at intervals?


Which "intervals" are you talking about?

 

Keep in mind:

  • Many of us cannot read Chinese text, so you better provide an English translation or comments in your block diagram.
  • When you want to attach screenshots then you should attach real screenshots, but not images taken using your mobile phone in front of your computer monitor…
  • Most often it is recommended to attach real code instead of images of code…
Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
Message 9 of 13
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Thank you for your kind reminder

 

I mean that my Memory DRAM reads the data from the first address to the last address one by one, and now I want to read the data from address 1, read the data from address 4 next time, and read the data from address 7 next time, each time with an interval of 3.

 

I read them sequentially and the output data was normal.

 

If I read it at intervals, the output gets messy. 

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Message 10 of 13
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