For / While loop first execution

[daveTW]

Why don't you run the VI with debugging mode ON? Click the bulb in the toolbar and then run. There you will see, what happens.

[daveTW]

Hello cwhwfebruaryeleventh,

I admit, I also had my difficulties with the FB node, when it was introduced. But it depends on your intuition whether you get used to it or not. So, give it a try.

I made a VI which contrasts the two approaches - FB node and Shift Register:

Run it with Light Bulb on and compare. Everything is as expected.

[wiebe@CARYA]

Of course FB nodes can to a lot more (not sure if that helps explaining them).

You can move it's init to higher level structures.

You can put the write in a deeper structure.

You can show the 'enable' input, making it conditional.

You can program the delay.

You can choose when it initializes.

I often prefer SR, simply because there are less strings (options) attached. They're older as well, so they have a bias for my understanding.

[daveTW]

You are right, and that's all cool stuff. But this is also possible with shift registers (to be honest, I'm not exactly sure about this, since I didn't know the "delay" feature). But I prefer wires, there is less magic and I can see, where the data goes and where it is altered.

This is in my opinion a question of taste and I don't want to open this discussion right here (seems off-topic for the TO's question).

So let's finish this comparison-question here.

[wiebe@CARYA]

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@daveTW wrote:

You are right, and that's all cool stuff. But this is also possible with shift registers (to be honest, I'm not exactly sure about this, since I didn't know the "delay" feature). 

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You can't do this with just a shift register. You'd need to actually program that functionality.

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@daveTW wrote:

 But I prefer wires, there is less magic and I can see, where the data goes and where it is altered.

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I'd go for simpler and easier to understand. 9/10 that's a shift register for me (but again, I'm biased toward the old stuff).

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@daveTW wrote:

This is in my opinion a question of taste and I don't want to open this discussion right here (seems off-topic for the TO's question).

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I can't really tell what your opinion is though 😁.

AFAIC, the topic is answered and as long as the FBN\SR stuff is constructive, why not continue?

I'm not having a flame war here. I don't even really have a preference.

BTW: Yes, SR can have a delay ('extract' the left wide of the SR):

You'd need to initialize all or none of the left outsize terminals. You have access to all delayed items, something a FBN doesn't have.

[cwhw112]

I did see the init value but moving the init into higher level structures is confusing

I dont really get the enable but could learn more by playing with it

similarly i dont see how to delay it

also i noticed i could move the node to the upper wire instead of lower and it functioned how i expected/wanted

in my LV for everyone book, the next few pages described how similar it is the a shift register so i probably could have waited/kept reading and answered my own question but good to have it 'on the line'

thank you for all the feedback

[cwhw112]

FB node on bottom wire

if you start with enable on everything works like normal (incrementing 9, 19, 29), turn it off and it increments once the first time then none (30,30,30,30), turn it back on and it increments as if just first opened incrementing 9, then 10, 10, 10

FB node on top wire

enable on

10, 20

enable off

21,21,21

enable on

30, 40

[altenbach]

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@cwhw112 wrote:

I did see the init value but moving the init into higher level structures is confusing

I dont really get the enable but could learn more by playing with it

similarly i dont see how to delay it

also i noticed i could move the node to the upper wire instead of lower and it functioned how i expected/wanted

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We are graphical programmers and sometime have trouble deciphering ambiguous text. You talk a lot about various "it"s. We would do better with a more graphical description.

The feedback delay is set in the properties.

[cwhw112]

Since someone referenced how you can expand down the left side of a shift register (to utilize values from previous loop iterations), I assume the FB node delay must then be number of iterations where no output comes from the FB node

[altenbach]

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@cwhw112 wrote:

I assume the FB node delay must then be number of iterations where no output comes from the FB node

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I recommend to avoid assumptions and look at the help!

There will ALWAYS be an output, but it might just be the default or initialized value. A wire cannot have "no output". (Even "empty string", zero, or NaN are "values".)