Hi
My system is based in two FPGA cards (7854R and 7851R) in a PXI controller (Labview 2013).
The system is used to get data from different sensors used in a multicylinder engine. All measurements depend on engine speed and two signals (TDC - 2 pulses/cycle and CAD-3600 pulses/cycle) are used. This signals are feed into the FPGA 7854R, called "master" and when data comes from those signals, then two different PXI_trigger channels are used to comunicate with the 7851R, called "slave". Those trigger lines "copy" the behaviour of the "real" signals, so the structure of both loops looks the same in both fpga.vi. Attached can be found pictures of this part of the code for each FPGA (files "fpga_master" and "fpga_slave"). These two signals generate variable used for sampling the rest of channels.
FPGA master: 9 signals in FIFO
FPGA slave: 3 signals in FIFO
Then, in another VI, the data is collected and stored in variable called "FPGA_data" as can be seen in the file "get_data_fpgas". Finally, the different channels are extracted in another vi, as can be seen in the file "extract_fpga_data". There a notifier is used for communication between vi, but the same behaviour appears if the data is extracted directly from the variable "FPGA_data".
This is how the system works. My problem is that, setting the same input signal for the AI0 in both FPGA, (which should correspond to positions 1 and 10 in the "decimated 1D array" seen in the files "get_data_fpgas" and "extract_fpga_data"), I can only see the data from the "master fpga" (position 1). Moreover and weirdly, the signal can be extracted from the position 11, but there is an small delay between the signals. However, I thought that nothing should be seen there...
Is method for collecting data from both fpga (see "get_data_fpgas) valid?? I mean first extract individual arrays from each FIFO reading and merge them again.
Thanks in advance
Regards,
Pablo
