Rif.: Getting a True or False signal from pulses

[JeeaaN]

Hello.

I am working on a project for my degree with LabView and LabView FPGA. I have a problem with a timer and how to count when there are pulses coming. I am measuring steps from a stepper motor which are generated as very short rising and falling edges or in other words pulses. I now need to make a timer when the steps are moving (motor runs), signal should be true, the timer counts up and when the steps are in hibernation (motor stands), signal should be false, the timer stops and if i run the motor again it continues the timer and so on. I have made a simple code and it works with a toggle switch but when i try to implement those steps onto the trigger, it doesnt work.  Am i even doing the step trigger correctly?

Thank you

[pincpanter]

What exactly does not work? You don't see Time OUT increasing as much as you expect?

It's hard to say by watching only at a small part of the program. The behaviour depends much on the program and motor timings.

Let's say your loop executes 1000 times per second and Steps changes every 10 ms: this means that the output from the boolean operator is only true 1 out of 10 loops, even if the motor is running, so you will loose 90% of the run time.

You need to clarify timing details in order to get a useful answer.

Furthermore, your program should follow a logic given by dataflow, where the data wires dictate the operation sequence. For example, you don't need the local for A, just wire the output from the Not Equal? operator to the code below: if you don't do so, you will never know whether the local will be read before or after the indicator value is set. I suspect that for Steps too you may drop the local completely.

Another suggestion for optimization: use a Case Structure to manage the boolean value. In the True case you will compute and add the delta time, in the False case you will simply pass the wire unchanged with no operations at all.

Although in this specific case the suggested changes may not make a lot of difference, there are other cases where this type of considerations is critical to get a working program.

[JeeaaN]

Yes, the Time OUT doesnt work as i want it. When i use a toggle switch as a trigger it works fine (test program in file Untitled 1). The pulses of steps are 150 microseconds apart. I tried the case structure variant but have found this kind of version which i posted before. I will upload the FPGA program which i am running on myRIO (FPGA Main my) and in which i want to implement that timer. Now what i need is when there are pulses i need an output with signal TRUE and when there are no pulses i need an output with signal FALSE. I know its not hard to make but i am loosing my mind over that. Been working on it for the past 4 days...

[JeeaaN]

I Have tried the option where i got rid of local variables but its still the same. Steps are counted perfectly but the "Time OUT" is still moving unpredictable and slow.

[pincpanter]

This is expected behaviour. My recommendations about locals were additional and did not address your main problem.

You should greatly improve the timing of your vi. I'm not experienced in FPGA coding, but I am sure that there are time sources far more precise than the tick count, which has 1 ms precision at best. Take a look at the Timed Loop structure, it can help you very much.

To make the time measurement reliable, you should find a mean to "pull-up" your boolean value for a while (150 microseconds or a little more) until you can guess that the motor is off because there are no more steps.

On the other side, if the interval between steps is really fixed to 150 microseconds, you may simply count the steps and multiply the counter value by this period.

[JeeaaN]

Thank you. I will try the Timed loop tomorrow. The time between pulses was 150 microseconds at a certain speed of the motor. I tried driving it at low speeds where one period of the pulses was 5 milliseconds but the outcome was the same. I was also looking at the stepper motor driver if it has any pin when its moving its a logic 1 and when its stalling its a logic 0. That would solve my problem completely but unfortunately it doesnt have one.

EDIT: The point is that my FPGA program is running on myRIO which has 40MHz clock and is very powerful. It doesnt have any problem counting all of the steps and their period is 50 microseconds so i dont think that its programs fault it cant count the timer correctly but the code itself. But thank you for the idea that i could calculate the time out of steps and the period. I havent even thought of that. For now i will measure the period with oscilloscope and calculate the time with the program. Thank you again.