Hello there!
I have been growing increasingly frustrated with the LabVIEW FPGA "High Throughput Rectangular To Polar".
I have a fairly straightforward task: for each sample of real and imaginary inputs, compute the magnitude and phase in a SCTL, exit the SCTL and forward the computed values. However, I'm noticing some behaviour that I don't understand.
To demonstrate, I have a simple VI:
When the inputs are FXP(18,5):
1. "output valid" is true at index=21 and yields the proper output (corresponding to the latency mentioned in the configuration panel).
2. "ready for input" is true at index 17, when the outputs are both 0.
When the inputs are FXP(16,5):
1. "ready for input" is true at index=17 and yields the proper value.
2."output valid" is true at index 19 and yields the proper value(corresponding to the latency mentioned in the configuration panel).
Based on this simple test and the documentation for the function, I would assume that I should wire "output valid" to the stop button of the SCTL. Perhaps the only reason why both "ready for input" and "output valid" work for case 2 is because the word length is shorter.
HOWEVER, I don't observe this behaviour AT ALL when I plug it into my real code: in a while loop I generate sine and cosine waves and, point by point, I compute the magnitude and angle in the SCTL. I've made sample code to demonstrate with arrays.
The first complex sample (i=0) is analysed correctly (the SCTL stops at index 21 with the correct output). For the next sample, the SCTL stops at 17, and the output is the same as for i=0. The next iteration also stops at SCTL index of 17 but the output is what should have been the output at i=1. On and on, the outputs are delayed by one while loop iteration.
I've tried understanding handshaking but I'm probably doing it wrong...I just can't make sense of this. My simple goal is for the function to return the correct output in the same while loop iteration. I don't care how many ticks it takes.
I really appreciate any input on this!! Thank you!
