Host to Target DMA FIFO underflow

[Michol]

Hello! I'm a beginner with LabVIEW.

I'm using Host to Target DMA FIFO to write desired data from the host and read that data on the FPGA for various processing tasks.

<FPGA>

<HOST>

When I wrote the code as follows, I observed that when writing one or a small amount of data from the host, the number of 'Empty Elements Remaining' stays fixed at (#Actual Depth - #Number of Data Written to FIFO), and the 'number of elements to read' on the FPGA FIFO stays fixed at 0. I understand that this happens because the write speed from the host is slow, causing an Underflow.

However, when writing a larger amount of data (approximately 400 or more) from the host, both the host queue and the FPGA queue become full, and data transfer occurs correctly.

The code I'm trying to write should allow data processing on the FPGA (should be read properly on FPGA) even if only 1 or 2 number of data are written from the host.

Is there another way to solve the Underflow problem and ensure that even 1 element of data is transferred correctly to the FPGA via DMA FIFO without increasing the number of data written from the host?

I fixed the Timeout to -1. 

Please Help me with various solutions!

Thank you so much. 

[ZYOng]

Have you tried using a non -1 timeout for DMA Write?

I would recommend you refer to the shipping example <LabVIEW>\examples\R Series\FPGA Fundamentals\Data Storage and Transfer\Host to Target Transfer\Streaming Data (DMA)\

[Michol]

Thank you for the reply. 

My goal for the final code is to give new elements from the DMA FIFO every 1 micro seconds. 

So, I have to use the Handshaking interface and give 'Output Ready' True every 1 micro seconds. 

I have a specific time I should make, so I believe changing the timeout is no use. 

I want all elements to be transferred repeatedly through the DMA FIFO even if I write a few number of elements & By using Handshaking Interface DMA FIFO. 

Is that possible?

[santo_13]

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@Michol wrote:

Thank you for the reply. 

My goal for the final code is to give new elements from the DMA FIFO every 1 micro seconds. 

So, I have to use the Handshaking interface and give 'Output Ready' True every 1 micro seconds. 

I have a specific time I should make, so I believe changing the timeout is no use. 

I want all elements to be transferred repeatedly through the DMA FIFO even if I write a few number of elements & By using Handshaking Interface DMA FIFO. 

Is that possible?

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1 micosecond deterministic handshake is not possible between host and target, given the host runs on Windows and being a non-RTOS, the execution of the Host side code is at the discretion of the OS.

[Intaris]

DMA is meant for larger data packets.

There is a certain amount of driver overhead associated with each and every DMA transfer.

Passing individual data points via DMA will be quite inefficient. Results will vary depending on hardware, but typically sending a single element via DMA takes nearly the exact same time as sending approximately 100 elements. After that is starts to scale linearly (i.e. 1% more per data point).

1 microsecond deterministic data rate is not going to work. At least not with feedback. If you want to pre-load the DMA buffer with data and then READ it at 1 microsecond intervals on the FPGA, that will work. But not send-response within 1 mcrosecond.