How can i avoid this build array? in FPGA

[Harishkanmani]

This VI is for FIR filter... Iam Ok with the outputs

but Optimization is an biggest issue here .

How can i replace those Build array since consumes much spaces

🙂 Happy Learning (:

[GerdW]

Hi Harish,

in FPGA you cannot use BuildArray to build a growing array like you do with that feedback node.

You need to use fixed-sized arrays in the FPGA!

[crossrulz]

The Build Array should not even be allowed in this situation since it causes an ever-growing array and FPGA requires arrays to be a set size.  And reading a FIFO typically invalidates the Single Cycle Timed Loop.

What exactly are you trying to accomplish here?  It looks like code that could very easily be done by the host and pushing it to an FPGA and right back up is going to use up more time than just doing it on the host.

[Harishkanmani]

x(n) = 1 ,2 ,3 ,4 ,5  ( Writing from Host & Reading in Target )

co-eff = 1, 2, ,3 , 4, 5 ( Writing from Host & Reading in Target )

iteration 1 : 1 x 1 = 1

iteration 2 : (2 x 1) + (1 x 2) = 4

iteration 3 : (1 x 3) + (2 x 2) + (3 x 1)= 10

iteration 4 : (1 x 4) + (2 x 3) + (3 x 2) + (4 x 1)= 20

iteration 5 : (1 x 5) + (2 x 4) + (3 x 3) + (4 x 2) (5 x 1)= 35

Filtered Output = 1 , 4 , 10 , 20 , 35 ( Writing from Host & Reading in Target )

[GerdW · Accepted solution]

Hi Harish,

you still don't explain why you want to implement this operation in the FPGA instead of having the host CPU do this small calculation:

I made this implementation with FPGA in mind, so only fixed-sized array and IndexArray nodes. All you need is to index the right elements from your x_n[] and coeff[] arrays!

[Harishkanmani]

Yeah sure...! before i started to implement in FPGA i have tried in Labview Host itself

but i need to get implemented on FPGA target 

here i cant use for loops right ?

So iam thinking of alternative ways 

anyway thank  you you for help

Stay smiled

[UMASO]

For loops can be used even in FPGA-targeted VI, where processing in For Loop is automatically parallelized at intermediate file generations.   However, only limited type of processing can be placed inside a For Loop, when it comes to FPGA.  

If you would like to implement FIR filter, there are various methods depending on your FPGA skill.  

An Introduction to High-Throughput DSP in LabVIEW FPGA

https://www.ni.com/ja-jp/support/documentation/supplemental/11/an-introduction-to-high-throughput-ds...

DFD (Digital Filter Design) toolkit allows you to design a filter step-by-step on host PC, including FXP assignments for filter data and coefficients.  Once you finished designing a filter on host PC, DFD generates a FPGA filter IP automatically.  You can refer to a help like following.  https://www.ni.com/docs/ja-JP/bundle/labview-digital-filter-design-toolkit-api-ref/page/lvdfdtconcep...

If you are familiar with LabVIEW FPGA, Xilinx FIR Compiler provides great usability to implmenet various high performance filters.  One of examples of articles on ni.com which explains about XIilinx FIR Compiler is this.  Polyphase Interpolation FIR Filter on FPGA with DFD and Coregen  (https://forums.ni.com/t5/Example-Code/Polyphase-Interpolation-FIR-Filter-on-FPGA-with-DFD-and-Corege...