How does FPGA block memory impact FPGA size in compile ?

[Vincent90]

Hi,

I am working on PXI 7841R cards and i'd like to know how can i determine the maximum "Requested number of element" of the memory block and wether it is better to work with differents memory blocks or only one...

Is it better to add several memory blocks of low number of elements... 1024 for instance

or 1 memory block with (let's say i have 10 signals to generate) 10240 elements ?

I have started with NI Example following :

http://www.ni.com/example/26548/en/

I feel like prefering multiple memory blocks to make easier the Memory block Read in a For loop with index loop as adress !

Vincent

[Vincent90]

Anyone already tried this architecture with block memories ?

My test is quiet not good because i already have treatment in other loops but my first ressource estimation is 35% FPGA ressources of 7841R using 6 signals with 65536 number elements each.

I don't think testing with only one block memory since 35% is enough to finish my need.

Vincent

[Vincent90]

Feel so lonely here...

I was cheking FPGA code only with pre-synthesis my FPGA code.

At the end, doing a full compile told me RAM was used at 660% with 6 memery blocks of 65536 elements each...

Where could we find RAM limitations in term of memory block or look up table usable ?

I have to find another way now, maybe look up table...

Any answer will be nice.

BR,

Vincent

[Intaris · Accepted solution]

How about posting some of your code so that we can have a look.  Bear in mind that the FPGA target you are using does not have many resources.

What width is the data going into your BRAMs?  Virtex 5 supports either 18 or 36 bit width.  Wider widths will require multiple BRAMs in order to get the data in and out, even if the usage is shallow. In addition, each BRAM can manage at most 32768 Bits (Not Bytes) so working out your width times your depth you can calculate how many BRAMs you will need.

Examples:

32 bit width x 65536 depth will use 64 BRAMs (1*32*65536 = 2Mbit, 2 Mbit / 32kbit = 64 BRAMS).

8 bit width x 65536 depth will use 8 BRAMS (Because the bit width is below 18, we can use each BRAM as two independent 18-bit BRAMS: 0.5x8x65536 = 262 Kbit, 262 kbit / 32kbit = 8 BRAMS).

40 bit width x 65536 depth will use 160 BRAMs (As the bit width is above 36 bit, TWO BRAMS must be parallelised in order to deal with the Bit width: 2x40x65536 = 5.2M, 5.2M / 32kbit = 160 BRAMS)

Given the fact that your FPGA only has 32 36-bit BRAMS (or 64 18-bit) then you need to make sure your data will fit.  The maximum bit width supported by this target for depth 65536 is 16.  This figure will be smaller in reality because some of the in-built functionality (DMA transfers and so on) already use one or two BRAMS.

[Intaris]

I need to make a slight correction to my previous post:

Each 18kbit BRAM can have an interface width of up to 36 bit whereas each 36kbit BRAM can have an interface up to 72 bit.  This affects the calculations in that the 40 bit calculation would only need 80 BRAMS, not 160.

[Vincent90]

Hello Intaris,

I'am glad someone care about this particular topic. I didn't get all you said.

My code is just the NI example i duplicated adding 6 memory block with 65536 elements on each memory block. So i don't understand from which bits width are you talking about... How can we configure Virtex 5 bits width (18 or 36)?

Example is not :

36 bit width x 65536 depth will use 75 BRAMs (1*36*65536 = 2.4Mbit, 2.4 Mbit / 32kbit = 75 BRAMS). ??

Why does my compilation tool indicate only 32 BRAMs maximum ?

I know that unfortunatly, my FPGA target doesn't have many ressources but i have to manage with it or find quicly another solution before buying this card.

My need is to generate 6 periodic analogic signal (square, triangle, sinus as differents frequencies).

Another test i want to do is to do the job with look up table but i would need 3 look up table (one for each kind of signals) but LabVIEW help tells it consumes lot of memory... more than memory blocks...

BR,

Vincent

[Intaris]

What you need to factor in is how wide the data is that you are storing in Block RAM.

So again, how wide is the data you are writing to your BRAM?  I can guess it's 16-bit because writing 65536 16-bit values requires 32 BRAMS (1*16*65536 = 1 Mbit / 32 kbit = 32 BRAMS).  Each 16 bit gets appended in the BRAM on a single bit boundary, there are no packing losses.  They do NOT all occupy 36 bits of space, itis not like sectors on a HDD.  Even making your data one bit smaller will increase how many of them will fit in a single BRAM.

The 36 bit I mentioned is only how much data MAXIMUM the BRAM can accept in one write (hardware limitation). It does not describe the packing of the data at all.

[Vincent90]

Thanks to your informations i finally gave up the 7841R LX30 PXI card for PXIe-7846R Kintex-7 160T.

This last one get out in 2016 17th July and is 10 time more efficient than PXI-7841R with same price. (but need LabVIEW2016)

Thanks Intaris for your detailled answer.

In a nutshell :

1) Look up table consumes less memory than memory blocks.

2) Ask yourself how wide the data is that you are storing in memory (memory blocks or Block RAM) and use Intaris formula.

Best Regards

Vincent

[Intaris]

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@Vincent90 wrote:

1) Look up table consumes less memory than memory blocks.

2) Ask yourself how wide the data is that you are storing in memory (memory blocks or Block RAM) and use Intaris formula.

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I don't think I understand what you're trying to say with respect to LUTs and memory.  I think you may need more clarification on that because the statement you seem to be trying to make doesn't sound right.

[Vincent90]

A LUT is a collection of logic gates hard-wired on the FPGA. LUTs store a predefined list of outputs for every combination of inputs and provide a fast way to retrieve the output of a logic operation.

A look up Table is a LabVIEW tool which make you play some points as you defined them into FPGA Target.

A Memory block is a LabVIEW tool which makes you play some points dynamically as you difined them into Host.

BRAM is the amount of RAM available on the target (unit : kBits)

My own test shows Memory Block use more BRAM than Look up Table and that PXI-7841R doesn't fit my BRAM need (thanks to your formula) so i choose the card that will fit my need. Thanks Intaris.