Hi, I am working on PXI 7841R cards and i'd like to know how can i determine the maximum "Requested number of element" of the memory block and wether it is better to work with differents memory blocks or only one...Is it better to add several memory blocks of low number of elements... 1024 for instanceor 1 memory block with (let's say i have 10 signals to generate) 10240 elements ? I have started with NI Example following :http://www.ni.com/example/26548/en/ I feel like prefering multiple memory blocks to make easier the Memory block Read in a For loop with index loop as adress ! Vincent

How about posting some of your code so that we can have a look. Bear in mind that the FPGA target you are using does not have many resources.What width is the data going into your BRAMs? Virtex 5 supports either 18 or 36 bit width. Wider widths will require multiple BRAMs in order to get the data in and out, even if the usage is shallow. In addition, each BRAM can manage at most 32768 Bits (Not Bytes) so working out your width times your depth you can calculate how many BRAMs you will need.Examples:32 bit width x 65536 depth will use 64 BRAMs (1*32*65536 = 2Mbit, 2 Mbit / 32kbit = 64 BRAMS).8 bit width x 65536 depth will use 8 BRAMS (Because the bit width is below 18, we can use each BRAM as two independent 18-bit BRAMS: 0.5x8x65536 = 262 Kbit, 262 kbit / 32kbit = 8 BRAMS).40 bit width x 65536 depth will use 160 BRAMs (As the bit width is above 36 bit, TWO BRAMS must be parallelised in order to deal with the Bit width: 2x40x65536 = 5.2M, 5.2M / 32kbit = 160 BRAMS) Given the fact that your FPGA only has 32 36-bit BRAMS (or 64 18-bit) then you need to make sure your data will fit. The maximum bit width supported by this target for depth 65536 is 16. This figure will be smaller in reality because some of the in-built functionality (DMA transfers and so on) already use one or two BRAMS.

LabVIEW

How does FPGA block memory impact FPGA size in compile ?

Solved!

@Vincent90 wrote:

My own test shows Memory Block use more BRAM than Look up Table and that PXI-7841R doesn't fit my BRAM need (thanks to your formula) so i choose the card that will fit my need.

"Memory" can be configured to use either LUTs or BRAM. The default case is Block RAM. But the exact same functionality can be implemented in LUTs. If configured according to the defaults, Memory will use BRAM, if configured to use LUTs, it will use LUTs. (BTW, LUT stands for Look Up Table)

@Vincent90 wrote:
A look up Table is a LabVIEW tool which make you play some points as you defined them into FPGA Target.
A Memory block is a LabVIEW tool which makes you play some points dynamically as you difined them into Host.
BRAM is the amount of RAM available on the target (unit : kBits)

Both memory implementations allow for re-configuration from the Host, and both can also be static is defined that way. These are NOT inherent usage differences between BRAM and LUTs. The difference between "look up Table" as you describe it and "Memory block" as you describe it are purely usage differences, they are not tied to the underlying imlementation of the memory. It is quite possible to define static memory with two read ports (and no write ports) to use them as look up Tables (your definition). This can be done independently of whether the implementation of the Memory is LUT ot BRAM. On the "Interfaces" tab of the configuration dialog for the Memory, you can choose to have two "Read" interfaces, this makes your Memory item read-only which corresponds to your definition of "look up Table".