How to add DRAM FIFO-128bit to the FPGA project?

[heel]

How do I add the DRAM FIFO - 128 Bit Memory Interface to a PXIe-796XR RIO module?

Above project is from one of the example projects. I know how to add DRAM but not how to configure it as FIFO 128bit as above.

Any guidance is appreciated.

[heel]

I really have not found a way to add the DRAM 128bit fifo to the design. Adding normal DRAM and target specific FIFO's and host-target FIFO's is easy, but the special DRAM implemented as a giant FIFO I could not find how to add. And I have searched the documentation - but obviously missed the key point. I use labVIEW 2013. Any hints are appreciated.

[WillD · Accepted solution]

Right click on the FPGA target -> Properties

Select DRAM Properties from left side of Popup.

Change mode of either bank to Socketed CLIP from LabVIEW FPGA Memories.

Hit OK.

The project will auto-update with the new DRAM, it will be blank.

Right click on the DRAM ->Properties

Enable

Select FIFO-128bit

[heel]

Thanks WillD,

The "Socketed CLIP" was the missing link. Thanks a lot.

May I suggest NI to review the documentation on how to add the DRAM 128bit FIFO. I don't find it documented when searching for  DRAM 128bit FIFO.