How to wrap the netlist file in a VHDL file?

[Michel_Gauvin]

Hello,

At this link http://zone.ni.com/reference/en-XX/help/371599L-01/lvfpgaconcepts/create_acq_clip/ it says "If you use IP defined using Verilog, you first need to compile this IP into a netlist file, then wrap the netlist file in a VHDL file."

I have this situation, but I don't know how to wrap the netlist file into VHDL file, anyone knows how to do this?

Thanks,

Michel

[Michel_Gauvin]

Hello,

I finally found out how to do this.  My collegue has developped a IP in Vivado which I needed to integrate into LabVIEW FPGA VI's.  We are using Vivado 2014.04, so the netlist of the IP has a *.dcp extension.  In the same directory you should find the component declaration which has a *.vho extension.  You should use the information in that file to create the wrapper.  The wrapper will have a *.vhd extension and will be used with the *.dcp to create your CLIP. Basically the wrapper creates an instance of the component.

I've inserted an example:

SelfResonatingCore.vho

SelfResonatingCoreWrapper.vhd

Michel