Inconsistent Execution from Host VIs

[wtribley]

LabVIEW 8.6.1, fpga 8.6.0, RIO 3.1.0 

I am building a test station using LabVIEW and the PXI7813R RIO board. I created the fpga application using the wizard which yielded LabVIEW project adc-rsr-rsg_controller.lvproj, PXI FPGA Target, adc-rsr-rsg_fpga.vi (inside a

lvlib) and adc-rsr-rsg_host.vi (inside a vilib). The plan was to implement timing and other low-level functionality in the fpga then use a host application for FFT and other analyses.

The fpga application works just fine, but it does not include the end-user features and data manipulation that we intend to do on the host. The dumbed-down host vi created by the wizard works fine. My host vis do not:they break the underlying fpga vi such that the unit under test stops working properly.

My host vis were created by two methods: rename the wizard-generated host vi, delete everything from the block diagram then insert my code (adc_rsr_rsg_ctl_panel-test.vi) or take a normal vi (created during requirements and design for front panel), bring it into adc-rsr-rsg_host.vilib, add fpga code based on code pasted in from the wizard-generated file. Both of these fail in the same way.

If you run a broken host vi, stop it then run the fpga vi it too is broken (this caused me to waste 2 hours thinking the unit under test was broken). However in this "broken" state if you run the wizard-generated vi everything clears up. the system works and you can subsequently run the fpga vi with no problem.

This has gotten me into hot water because this system needs to ship, the software is completely broken. Any help appreciated.

Regards,

Bill

[DiscoBall]

Hi Bill,

I have just seen your forum post and will be looking at your project files soon. However, if you are in need for more immediate help, I suggest
giving NI Phone Support a try.

Did you get any errors from your VIs? Can you determine when you application stops running?

[wtribley]

I just read a reply to email support that was sent last Friday after I left the office. Below is an excerpt from what David 

Ladolcetta wrote, I am going to try it now after I figure out how to simulate the hardware that shipped on Friday 😉 . Good training, we should be able to test our software without target hardware.

Regards,

Bill

After looking at the VIs again, I noticed that one major difference between the two VIs is in your Open FPGA Reference function. In your adc-rsr-rsg_ctl_panel-test.vi you have the Open FPGA Reference function set to Run the FPGA VI automatically (right click the function and select "Configure Open FPGA VI Reference", the option is "Run the FPGA VI"). In the host VI from the wizard they have this unselected. This might be a problem because you are telling the FPGA to run, reset, and then run again via the invoke node.

Other than that, the two VIs seem pretty much the same, so I have a feeling this is what is causing the problem. Try changing this and running again.

Let me know if this solves your problem or if your FPGA VI is still being interrupted. If so, I can try researching this problem more and finding another solution for you.

[wtribley]

I just checked the code, somehow on my system the box to run the fpga code is unchecked on all the versions I have tried. So, it is something else. I have to work on another project today, will get back to this as soon as I can.

[DiscoBall]

Since you are working with David it will be best for you to continue working with him. If you do find a resolution please to post it on the forums.

[wtribley]

Will do, I am hoping to have hardware to work with next week.