Issue with sampling from the 9212 using the FPGA

[cirrusio]

That last response was incorrect.  So, as @GerdW recommended, I broke out the TC readings into a separate loop on the FPGA and there was no change.  I removed all of the readings on the RT side except channel 0 and CJC0 and the time to execute across this node is > 800 ms (the rest of the loop according to the loop timer takes an extra 1 ms). Why is this?

[cirrusio]

Seems that this is not an issue with the FPGA - the loop collecting this data is executing at ~1/40th of a second (1.28 Mticks) but I am still getting a return that is 3-4 seconds.

[cirrusio]

So, I finally had to revert to @crossrulz suggestion to condense all DI into a single number.  It seems that there is some weird issue with the number of controls on the front panel where the FPGA will not behave as expected when there are too many controls there.  I am not sure what the threshold is, but I was able to toggle this behavior by adding and removing inputs.  Wish there was more information on this.  This is not an ideal solution for me as the application is distributed so keeping track of a single number is not straightforward...

[Haricharan_P]

Hi GerdW,

I want to know how the voltage resolution can be calculated, which is not implicitly mentioned in the manual.

Thank You,

Haricharan

[GerdW]

Hi Haricharan,

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@Haricharan_P wrote:

I want to know how the voltage resolution can be calculated, which is not implicitly mentioned in the manual.

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Resolution = voltage range / number of bins.

Example: 16bit ADC with a ±10V range gives 20V / 2^16 = 0.3052 mV.

Remember: resolution is something completely different than accuracy!