LABVIEW FPGA running Sub Vi without Host

[RubiMesh]

I don't think.

The FPGA build includes single bit-file where sub-VI-s are added through the Build Specification:

and at the runtime the SubVi-s are called directly:

[Intaris]

"The FPGA build includes single bit-file where sub-VI-s are added through the Build Specification:"

Please explain what you mean by this, your descriptions are very vague and cryptic. It's almost like you're obfuscating on purpose.

[RubiMesh · Accepted solution]

It looks that I found the solution.

To add the subVI to the bitfile it shall be defined as pre-allocated clone in execution properties:

Other parameters shall be set too to enable active front panel for this subVI

[Intaris]

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@RubiMesh wrote:

It looks that I found the solution.

To add the subVI to the bitfile it shall be defined as pre-allocated clone in execution properties:

-pic-

Other parameters shall be set too to enable active front panel for this subVI

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This makes no sense to me at all.

This all sounds like it's all on the RT system, not the FPGA at all.

[RubiMesh]

The timing is very tight (the UART runs at ~400K and responses sent in 10-20 uSec) cannot be achieved on the RT