LabVIEW
LVFPGA - Process "Translate" failed
Solved!
Hi
Currently using LVFPGA 2013 SP1
I'm used to compile my code oftenly, which happens to be necessary when using the FPGA module
Today, I started to get a "Process "Translate" failed" message in the Xilinx Log while trying to compile. The compilation is not aborted and still running
Same problems have already been listed here and here, and issue is supposely fixed in LVFPGA 2014 (associated CAR 428544)
We won't probably change IDE version to 2014 😞
So that here follow my questions:
1. Is the compilation process going to generate a working bitfile as this post suggests ?
2. Any information about the problem (why is it happening?). Couldn't find any helpfull CAR description
3. What elements in the code I'm trying to compile may lead to the compilation to fail/take that much time ? Any recommendation/workaround ?
Thanks for help
Mathieu
4 hours later, the compilation succeeded, although I'm using very small part of the FPGA resources
Device Utilization
---------------------------
Total Slices: 2,0% (293 out of 14336)
Slice Registers: 1,3% (372 out of 28672)
Slice LUTs: 1,4% (395 out of 28672)
Block RAMs: 0,0% (0 out of 96)
Please advice NI
Same issue with 2014 (regarding the translate process failed message), so that it happens not to be linked to other issues
There must be something we're doing wrong
Currently in touch with NI
As a follow-up, in case someone ends up reading this post, with a similar issue
- It happens that the previously listed CAR is linked to FIFOs. I have no FIFO in my code, so that my problem is not linked to this CAR.Compiling in LV 2014 still shows the same message
- There are several translate processes within the same Xilinx compile process. First one may fail, but the second one should be successfull. This is expected; the compile process is behaving as expected.
We still can't explain why my code took 4 hours to execute once, whereas it only takes 1 to 2 hours now
