LabVIEW FPGA Error: NI-Farm: Client received unexpected or bad data from the server.

[JJMontante]

Attempting to "build" the FPGA causes NI-Farm error. See attached picture for error dialog messages.

"An error occurred attempting to connect to this compile server. Details: NI-Farm: Client received unexpected or bad data from the server." It also fails to connect to the NI server, and no capabilities are shown in the FPGA Compile Worker 2017 window.

Windows 7 Pro, LabVIEW 2017, LabVIEW FPGA 2017, Xilinx Compile Tools Vivado 2015.4, Targeting PXIe-7971R, custom FAM

Background:

1. Created a labview FPGA project and application. FAM has 2.5 years of successful LVFPGA builds.
2. Created buildspec for the FPGA
3. Successfully built the FPGA multiple times over the last few weeks.
4. After a few weeks, needed to rebuild.  I can identify no changes to my system configuration (LV Software, hardware, or tool conflicts).
5. Now getting this error 100% of my attempts to build.

Observation: Opening up the NI Compile Worker capabilities used to show a few versions of the Xilinx Compile Tools, but now is completely empty. After each of the following steps, I attempted to build. No change.

1. Close and re-open project
2. Reboot computer
3. Opened NI software manager, and chose to "REPAIR" LVFPGA module, NI RIO, NI Farm, Xilinx Compile Tools 
4. Follow steps to "clear" NI Auth and NI servers/services per https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019N2vSAE&l=en-US
5. Attempted to create a new project, from scratch, with a simple input->increment->output in a SCTL.  Build fails in the same manner.  I am able to replicate the error on multiple projects.

Thanks for any help.

EDIT: attached Max report.

[JJMontante]

Other things I have attempted:

1.  Installing LV2017 updates. No improvement

2. Installing fresh LV2019 with FPGA modules and tools. No improvement.

3. Wireshark review of TCP port 3582 traffic when attempting LVFPGA compile.  No packets observed on my ethernet interface.

In the short term, I've found a workaround:

1.  Create a Vivado project export.  reminder that the Xilinx build tools hate path-names with spaces in them. You may need to update the Vivado Export configuration to choose a different destination path.

2.  Open vivado, (right click the export in Build spec if necessary)

3. Click "Program and Debug" in the Flow Navigator tree on the left. 

4.  Click "Generate bitstream".  

Created the .lvbitx and sent to my teammate for incorporation into our application.  

I will post once I have a fix for the original problem.

[JJMontante · Accepted solution]

Solution:  

I set new Windows system environment variables for HTTP_PROXY and HTTPS_PROXY in order to get access to a public repo for a Python install related to another project.  I removed those environment variables, since they were no longer necessary and build works.

[GatorChomp]

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@JJMontante wrote:

Solution:  

I set new Windows system environment variables for HTTP_PROXY and HTTPS_PROXY in order to get access to a public repo for a Python install related to another project.  I removed those environment variables, since they were no longer necessary and build works.

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For context on why that would have an impact: The LabVIEW FPGA Module (which is the "client" for the compilation) and the Compile Worker both communicate with each other through a localhost web service located by default at port 3582. Port 3580 is used to locate the web service since it might not be at the default port if a user changed the configuration of the NI System Web Server. If localhost HTTP traffic were being rerouted by a proxy, it would prevent that link from behaving properly.