LabVIEW FPGA Reported Error

[hemanthsurya99]

I am getting this error whenever i am playing with VI in labview software.

[GerdW]

Hi hemanth,

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@hemanthsurya99 wrote:

I am getting this error whenever i am playing with VI in labview software.

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So the error is in the way you "play" or in your VI.

We cannot comment any of both options because of missing information...

[hemanthsurya99]

yes whenever i am playing vi then i got this error. pls let me know what kind of info you need to solve this.

[hemanthsurya99]

How to identify which is causing this error to pop up.

[ZYOng]

Please post your code so that we can know what might be wrong.

[hemanthsurya99]

its huge code that too confidential. can you predict where I'm going wrong need some inputs so that i will check it out.

[rolfk]

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@hemanthsurya99 wrote:

its huge code that too confidential. can you predict where I'm going wrong need some inputs so that i will check it out.

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You are asking us to do something similar than to diagnose what defect your car has when it’s beeping.

Beeping where? Is a dashboard light blinking? Or is it the tires screeching when you go fast around a corner? Does it beep as soon as you start the engine or rather when you do something specific?

You realize that LabVIEW can execute your program in single step mode and you can then go into the subVIs and see which function is exactly generating that error?

[hemanthsurya99]

Issue solved by myself. In my RTL design the reference clock is not connected internally becoz of which labview is throwing error. Issue solved.

[hemanthsurya99]

Can anyone help me in this regard?
My top file is written in Verilog code. How can i make labview software to support verilog hdl?

Thanks.

[Terry_ALE]

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@hemanthsurya99 wrote:

Can anyone help me in this regard?
My top file is written in Verilog code. How can i make labview software to support verilog hdl?

Thanks.

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I cannot find a good reference but Verilog must be wrapped in VHDL to be called.  In other words, the top level cannot be Verilog.