LabVIEW FPGA property node input not fixed size

[IhmeKyselijä]

Hi,

I am writing a script for my PXIe-5774 fpga that takes input and calculates it's fft. Before that I need to do some windowing and I was suggested (https://forums.ni.com/t5/LabVIEW/FPGA-FFT-windowing/m-p/4307880) I use a circular buffer to create this window function that I am reading from BRAM and multiplying my signal with that data. My problem is that I can't compile the code because the output coming from the circular buffer is not fixed size (even though it should always output an array that is 16 elements. Right?) and  the property node requires it's input to be of fixed size (also the downstream fft block needs that too). How can I combat this issue? A picture of my code is below:

The rest is an example found in "NI Example Finder" >> "Hardware Input and Output" >> "FlexRIO" >> "Integrated IO" >> "Getting Started" >> "Getting Started FlexRIO Integrated IO.vi"

Thank you:

Aarni

[raphschru]

Hi,

You will maximize your chances of being helped if you could attach your VI saved for LV2020 or LV2021 (Go to your VI -> File -> Save for Previous Version). Also, if it is confidential or too big to be posted, remove everything that is not related to the problem and try to come up with a minimal VI that reproduces the compilation error.

Regards,

Raphaël.

[crossrulz]

Arrays in an FPGA must be fixed size.  Right-click on the output array and there should be an option to set the array size.

[UMASO]

Feedback nodes right after FIFO read may be the problem.  The feedback node after FIFO read may not propagate information of array size.  Please try to initialize feedback nodes of array data by doing just the same as below.  

[Intaris]

Yes, feedback nodes seem to mess with the "fixed length" array propagation.

I ran into this last week with a coworker. I was astounded to find out that it was a feedback node preventing code from working properly. Specifically, we has controls and indicators on the FP which were set to dynamic, but the instances used in the FPGA compilation complained that the array size was not constant when it clearly was.The actual array length was not being propagated from the control through the feedback node.

This is clearly a bug in my opinion.