LabView FPGA Reading Block Memory in SCTL - Fast

[niederlj]

Is it possible to read more than 1 value from Block Memory in a SCTL ?

I need to read 8 I16 Values from Block Memory and  store them in an Array within about 20 Cycles maximum. If I call the VI within a loop (8 Times), it takes about total of 52 Cycles. The Sizes of the array (indexed) is 8.

The total size of the Memory is 2* 7200 I16 Values.

Br,

Johannes

[T-REX$]

Well, without knowing more about what you're trying to do... my first two thoughts are to bit-pack the 8 I16 elements into 2 U64 elements, or to split your single memory item into 8 memory items, and access them in parallel.

[nathand]

Looks to me like the problem is the FOR loop overhead. If you remove the FOR loop and instead allow the single-cycle timed loop to execute several iterations, you can get the speed you need since you can read one memory element per loop cycle.

[niederlj]

I removed the for Loop. Now I am down to 17 Cycles and that is fine so far.

The Sub-Vi in the attached PNG is just a devide by 2 Function.

FYI:

I am simulating cylinder pressure of an engine (writing Values from HOST to analog output on FGPA) with max. 8 cylinders, an resolution with 0,1 ° Crank angle and a maximum Speed of 12000 RPM. All 8 Channels are using the same 7200 Values as a base for the Crank Angle Related Pressure. Outside the mentioned Loop I am transferring the Data from Host to FPGA each time I have a new operating point (Speed and Torque). I need to execute some calculation within the FPGA on the base data, in order to get more realistic outputs. And currently I had to free up some time for that.

THANKS!

[nathand]

Be careful of one thing in that VI - the required feedback node after the memory read means the value you are inserting into the array is one cycle behind the memory address. To get 16 values you need to iterate 17 times, discarding the value from the feedback node on the first iteration.

[niederlj]

Hi nathand!

The loop looks like working as it is.The loop condition “Stop if > 15” means 17 iterations (i start with 0 and stop with a value of 16). Correct ?

I am replacing the value in the Array with "Replace array sub set". 2 Times at each index. 2nd Time it will overwrite at the same index position with the correct value. The feedback node is required in order to use it in SCTL.The Sub VI devide by 2 could be replaced with a logical shift.

The more interesting aspect for me was during prev. test:

Memory must be set to “Never Arbitrate” or “Arbitrate if Multiple Requestor Only” in SCTL usage. I used the sub vi only for reading 1 single value out of the Memory in SCTL. So, stop the vi after 2 iterations. I set the vi execution mode to “Preallocated clone reentrant execution”. Calling the Sub VI 8 times in parallel, in order to read all 8 values. In FPGA execution “Development Computer with Simulated I/O” everything was fine. Compilation on FPGA Target also was OK.

But in fact, this creates a strange behavior of the values, visible only in real FPGA Target mode.

Because of parallel execution “reading memory” (which is not allowed according to online help).

I would expect an error message during compilation on the FPGA Target.

What do you mean ?

[nathand]

Sorry, I did not mean to imply that there is a problem with your code, just that you needed to be aware that there could be a problem. Obviously I can't see what's inside your subVI, and didn't realize it's a divide by 2. However, if you're going to take the divide by 2 approach, you should have 18 loop cycles, right? Not 17?

Of course, if you're trying to save loop cycles, you could do this in 9 iterations by inserting each element into the array one iteration after you read it from memory. I thought that was what you were trying to do, which is why your code made me think there might be a problem. If you do take that approach you need to be more careful about how you handle disabled channels, of course, but you can basically do it by adding a feedback node on the wire going into the index of replace array subset.

I can't see the other cases in the case structure, but could you simplify by using boolean logic instead of nesting case structures?