LabVIEW
Labview FPGA and DIO CLIP (sbRIO target)
Hello, I have an sbRIO board and i want to pass a clock through FPGA from one pin to another. I'm routed a clock to port, say DI (DIO63) and expecting it on another port, say DO (DIO46).
If a use direct connection of one DIO to another in an sctl (all DIOs are configured with 0 synchronization registers for write and read) clock is passing normally and I see it on DO:
Now I want to use a clip for this task. I've created a basic vhdl file:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity user_ip is
port (
clk_in : in std_logic;
clk_out1 : out std_logic
);
end user_ip;
architecture rtl of user_ip is
begin
clk_out1 <= clk_in;
end rtl;
Imported it to project using Component-level IP wizard (see below) with default configs and dropped it do diagram:
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<!-- National Instruments recommends that you do not change this CLIP declaration file outside of the Configure Component-Level IP wizard. You can modify this declaration file on the Component-Level IP page of the FPGA Target Properties dialog box. -->
<CLIPDeclaration Name="user_ip">
<FormatVersion>4.2</FormatVersion>
<Description/>
<TopLevelEntityAndArchitecture>
<SynthesisModel>
<Entity>user_ip</Entity>
<Architecture>rtl</Architecture>
</SynthesisModel>
<SimulationModel>
<Entity>user_ip</Entity>
<Architecture>rtl</Architecture>
</SimulationModel>
</TopLevelEntityAndArchitecture>
<SupportedDeviceFamilies>Unlimited</SupportedDeviceFamilies>
<InterfaceList>
<Interface Name="LabVIEW">
<InterfaceType>LabVIEW</InterfaceType>
<SignalList>
<Signal Name="clk_in">
<HDLName>clk_in</HDLName>
<HDLType>std_logic</HDLType>
<Direction>ToCLIP</Direction>
<SignalType>data</SignalType>
<Description/>
<DataType>
<Boolean/>
</DataType>
<UseInLabVIEWSingleCycleTimedLoop>Allowed</UseInLabVIEWSingleCycleTimedLoop></Signal>
<Signal Name="clk_out1">
<HDLName>clk_out1</HDLName>
<HDLType>std_logic</HDLType>
<Direction>FromCLIP</Direction>
<SignalType>data</SignalType>
<Description/>
<DataType>
<Boolean/>
</DataType>
<UseInLabVIEWSingleCycleTimedLoop>Allowed</UseInLabVIEWSingleCycleTimedLoop></Signal>
</SignalList>
</Interface>
</InterfaceList>
<ImplementationList>
<Path Name="user_ip.vhd">
<TopLevel/>
<MD5>dd489bfd1eb7be971758ad462c35b6fc</MD5>
<SimulationFileList>
<SimulationModelType>Same as synthesis</SimulationModelType>
</SimulationFileList>
</Path>
</ImplementationList>
<NumberOfDCMsNeeded>0</NumberOfDCMsNeeded>
<NumberOfMMCMsNeeded>0</NumberOfMMCMsNeeded>
<NumberOfBufGsNeeded>0</NumberOfBufGsNeeded>
</CLIPDeclaration>
This implementation is running, BUT I do not see any activity on DO (all DIOs are configured with 0 synchronization registers for write and read). What's the problem? What do i need to add/remove/change in a vhdl file and overall clip to make it work?
Konstantin.
Hi Konstantin,
There are a couple of things that jump out at me with your LabVIEW FPGA code. You mentioned that you set the synchronization registers to 0 for the DIO, but you didn't mention doing this for the CLIP. I would recommend setting the synchronization registers to 0 for the CLIP as well. You can access this option by right-clicking the CLIP in the Project Explorer window and selecting Properties.
Another thing that jumps out at me is that you have a True constant wired to the Conditional Terminal. I would recommend using a False constant instead of a True so that the loop runs more than one time.
I believe the combination of these things is causing your issue. Since the loop only runs once then there aren't enough iterations for the signal to get through the synchronization register. We have run your CLIP on a device here and we don't encounter the problem when changing these two things.
We often find it helpful to use controls and indicators for troubleshooting purposes with CLIP. We used the VI shown in the picture below to initially trouble shoot your CLIP.
Hopefully this information is helpful!
Hi Josh!
Yes, I've totally forgotten about synchronization registers in CLIP nodes. Let's continue some sort of investigation.
Now suppose we use the same CLIP and now the number of all the synchronization registers of DIO and CLIP nodes are 0. For tests I've connected 10 Mhz oscillator to DIO63.
Consider this code (yes, the True constant is wired to the Conditional Terminal):
It will work: we will see continuos 10 MHz clock on DIO46. And this will be true regardless of SCTL rate (default 40 Mhz or down to 2.5 Mhz) UNLESS we change the number of synchronizing registers of output enable for our DIOs from 1 to 0. Then the code above won't work and we will see logic low on DIO46 every time we load a bitstream to FPGA.
Now lets move the code above out of the SCTL:
When the synchronizing registers of output enable for our DIOs is 1 the code works an interesting way: we will see logic low or logic high on DIO46 from one load to another load of a bitstream (or system reset). When the synchronizing registers of output enable for our DIOs is 0 the code won't work at all: we will observe a logic low on DIO46 always.
Can you explain:
1) Why do we need to use the number of synchronizing registers of output enable = 1 to make codes above work?
2) Why do we need an SCTL running ONE iteration to make code with a CLIP work and why code with a CLIP outside and SCTL won't work properly? if we have zero triggers on digital path:
we do not need any iterations to pass a signal form input to ouput only routing delays will arise
3) Why so strange behavior of a code outside an SCTL with the number of synchronizing registers of output enable=1? Like a code one shots one single event on input and then stops (consider the 2'nd question)?
Konstantin.
