Large FPGA vi compiled in LV 2009 but not 2010

[all477]

Hi Folks,

I recently upgraded from LabVIEW 2009 to 2010. My very large vi barely fit on the chip using 2009, but it fails in 2010. Specifically, I get the following errors:

ERROR:Pack:2310 - Too many comps of type "DSP48E" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device.

I attempted to recompile several times in hopes of getting to a good solution. Has anyone else experienced this? Thoughts?

thanks!

Software/hardware: Windows 7, LV 2010 SP1, PCI-7852R

[Dragis]

I'm curious to know what the DSP48 usage was in 2009 vs. 2010. The compilation status window should show you the resource usage.

[all477]

Thanks for your reply. Can you help me find this info? Searching for "DSP48E" in the Xilinx log only returns the line where the error occured.

In the meantime, I've removed a significant chunk of the code (decreased functionality) and attemped to recompile; same error.

For completeness I've attached the txt file of the Xilinx log.

[Dragis]

Great, that log file was helpful. Could you post a similar log file for 2009? Then I can look for discrepancies. 

[all477]

Hi,

Thanks for thinking about my problem. I called NI, and it turns out that there is, in fact, a known issue having to do with the way that NI has handled a change to the Xilinx tools. According to the application engineer, the workaround is to use high-throughput multiplies instead of ordinary ones. For some reason, this known issue isn't listed with the others. I asked that it be added, as having it on the list would have saved me quite a bit of trouble.

Trying the workaround now... fingers crossed!

[Dragis]

Thanks for the update. If the workaround does indeed work, please post it here, or at least a link to some documentation, so others can find the answer down the road.

[all477]

I wound up going back to LV 2009 for now. I might give it another shot when my institute gets its site licence for 2011 in a few weeks.

[Austin_S]

As all477 has mentioned, this problem does indeed lie in the Xilinx compilation tools and is something that our R&D team is aware of.  This issue has been addressed in CAR (Corrective Action Request) #276311. 

Also, as mentioned, there is a workaround that isn't a guaranteed fix, but has appeared to solve the issues that we've seen on this so far.  You'll need to configure your High Throughput Multiply functions to "Look-Up Table".  This can be done following steps 6-9 below.  If you're using the FFT VI on your FPGA Target, you'll need to follow the following steps to find these:

1. Open up your "Fft.vi" in the subVIs folder.
2. On the block diagram, right-click on "FFT" and select "Convert to SubVI."
3. Once the subVI appears, open up its block diagram. There will be another blue-bordered ExpressVI with "FFT Core" in the icon.
4. Right-click this VI and select "Open Front Panel." In the pop-up window that follows, click "Convert."
5. Once this VI is converted, view its block diagram. There's a lot of code in here, but we're looking for four instances of the "High Throughput Multiply" function. They will be labeled "FXP Multiply 1," 2, 3, and 4, and are vertically aligned.
6. Right-click one of them and select "Configure." On the right side of the configuration window, under "Pipelining Options," you will see "Auto" is selected under "Implementation resource." Change this to "Look-Up Table."
7. Don't forget to make the change to Look-up Table for all four instances of the multiply function.
8. Save everything (you'll have some new subVIs to save, as well as altered upper-level VIs).
9. Give the compilation another try.

[Thoric]

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@Austin S wrote:

6. Right-click one of them and select "Configure." On the right side of the configuration window, under "Pipelining Options," you will see "Auto" is selected under "Implementation resource." Change this to "Look-Up Table."

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Hi Austin,

I have this exact problem having upgraded to LV2011, my FPGA VI doesn't fit anymore showing error ERROR:Pack:2310 - Too many comps of type "DSP48E" found to fit this device.

Unfortunately, when I examine my High-Throughput Multiply functions, the Implementation Source dropdown list is ghosted out. I can make it available by setting the Number of Pipelineing Stages to more than zero, but I'm not sure I want pipelining enabled? From what I understand about pipelining this will cause a hysteresis in the function (as shown by the information description in the configuration pane declaring the function cycles count as 2 and no longer 1).

Is there another way to get the LUTs option? Or is there another way to encourage the Xilinx compiler to use flip-flops over DSPs when there aren't enough?

Thanks,

[Austin_S]

Hi Thoric,

I've contacted one of the members of our R&D team to get a little more insight into this and why we can't select Look-up Table without enabling Pipelining.  I'll post back once I have a little more information to pass along about this.