Minimum sampling time

[Harjot]

I am using NI CRIO 9014 real time controller along with NI 9474 and NI 9222 modules. I am using FIFO to plot the current sensor input to one of the analogue inputs. I am using default clock rate of 40MHz. I am using four channels of Ni 9222 for the data measurements (hence sampling rate per channel should be 500/4 = 125S/s). However in practical I get a smapling rate of 75 S/s as displayed by the host window. So my sampling time comes out to be 40MHz/ 75S/s *25ns=13.3 us. In my application I want a reduced sampling time in the order of 1 us . Can somebody tell how can I achieve this ? 

[Riepld]

H Harjot,

i hope the following link can answer your question

Why Does User Controlled I/O Sampling Acquire Faster than an I/O Node?

http://digital.ni.com/public.nsf/allkb/5250C3AAE0CBAAE68625777F0072438E?OpenDocument

Best regards

[Harjot]

Hi Riepld 

I already saw this documentation and used user controlled I/O nodes along with single step timed loop. But still I could not reduce the sampling time...

Regards

Harjot

[0utlaw]

Hi Harjot,

Could you elaborate on what you mean by "Sampling rate of 75 S/s as displayed by the host window"?  Are you running the host VI on the RT controller interactively? Communicating over the network?  Where does this sample rate come from/ how are you benchmarking the application in question?  Are you referring to a shared variable RT FIFO or an FPGA DMA FIFO? What does your FPGA code for the four-channel acquisition look like? (upload if possible).

The 9222 should be capable of a full 500 k samples/sec on each channel (no need to divide down, this is a simultaneous sampling module, check the specs), so it seems unlikely that you're running into a hardware limitation.

Regards,

[Harjot]

Hi Tom 

Thank you for getting back to me promptly. Here I goes to the specifics. We have three while loops running on the fpga (CRIO-9111). What we have found so far is the way these loops are programmed impact the sampling time of acquisition since we have a closed loop configuration

We are streaming the data via DMA FIFO (see fpga.png). This is the first loop of our fpga. The other two works on the analog channels (NI9222) and we stream the data to the host computer as you can see from RT.png attached. 

We created an user interface to monitoring exactly the time each tasks on the fpga is taking. We measure that in ticks (see the right hand side of of third image attached (GUI.png) 

User can set (from the left side) and the actual sampling rate (from the right side ) that is given by the Sampling Rate to Loop time.vi. In this example we set the sampling rate at 500kS/s which giving 2us time step. However, the actual time step is determined by 770 ticks resulting from the loops we have on the fpga.

That means our sampling rate deteriorate drastically because of coding the close loop application we have

One thing to note is that our fpga is rated to 300kS/s. We suspect that the result of our almost 75kS/s is because 300kS/s/4=75kS/s. Let me know if we are on the right track here. 

Is there a way to bring the sampling rate to the advertised values?

Thank you in advance..

Harjot

[Craig_]

You should group your FPGA IO Reads into a single node. Currently you have this:

You should do this instead:

[Harjot]

Hi Craig

I have tried the program with your suggested modification. By using single node to read analogue inputs, I was  able to bring the sampling rate at 125kS/s. giving a sampling time of 8us.I was wondering that if this is the minimum that I can achieve with this module or there is still possibility to reach a datasheet value of 500kS/s/channel

Thanks.....

Harjot 

[[dk]]

If you sample just one channel on the 9222 what is the highest rate you can achieve?

[Harjot]

Hi Daniel

Right now by using the user controlled I/O sampling , I am getting a rate of 220 ticks that is equivalent to a sampling time of 220*0.025 us = 5.5 us. This is the minimum that I could achieve but it is still higher than 2us.

Regards

Harjot

[[dk]]

Have you run the NI 9222 User-Controlled IO Sampling.lvproj example? I am curious to see what sampling rate you get from the example as a comparison. The example can be found from LabVIEW by navigating to Help » Find Examples and then Hardware Input and Output » CompactRIO » Module Specific IO » Analog Input » NI 9222 User-Controlled IO Sampling.lvproj. Run this and compare the results.