Minimum sampling time

[Harjot]

Thanks Daniel for showing interest in my problem and writing on my post.

In our program I am using the acquired data to control the switches by using hysteresis control. In nutshell I am using the acquired input in the program logic to control the  DC -DC converter operation. When I used NI 9222 User-Controlled IO Sampling.lvproj example( without any processing on the data) I achieved samping rate of 500kS/s/ch  (sampling time -2us). However when I applied the same user controlled I/o logic to my application , I got a sampling time of 6us

(240 ticks*0.025us). 

I feel that the time elapsed in closed loop operation with the program logic is affecting the sampling rate.

Please share your views on this problem.

Regards

Harjot

[[dk]]

Is the FPGA image you posted earlier the same code that you are using currently? If not, could you please post your code? What are the inherit differences between the User-Controlled IO Sampling example and your code?

[Harjot]

Hi Daniel

As I mentioned I have modifeid the code wrt my previous posts to consider user-controlled IO sampling .Please see the attached imgaes showing the previous and updated code.

[[dk]]

The only thing that I notice immediately is that the DMA FIFO data type is set to a single precision rather than fixed point. I would change that and see if there is any performance difference.

What happens if you use the FPGA code from the example with your host interface code? Do we still see the lag in sampling rate?

[Harjot]

Hi Daniel 

Thanks for your prompt reply. I didn't try  to run example code with the host interface code. Only thing I tried was to modify my code as per the example and  it  resulting in a sampling time of 6us ( as per my last post). The complete FPGA code includes two loops , one for reading the input channels for FIFO  and the second loop to apply hysteresis current control (as you can see in the attached file) . So here I am accessing the same input channels in two separate loops. Can this be a reason for sampling delay? If yes, would like to you propose a solution to this.

Regards

Harjot

[Craig_]

You should have a single IO Node for the module that reads from every channel. Putting it in a different loop means that they will be trading off reading data from the card.

[Harjot]

Hi Craig

Thanks for the input. Can you please suggest how I can read  from a single node while using the read data in two separate loops..I will appreciate if you can post any example code for the same.

Regards

Harjot

[[dk]]

I would look into writing the data from the top loop into either another FIFO (VI-Defined FIFO or target scoped FIFO) or register. This way we can read the data in another loop and not slow down the sampling rate by using multiple I/O nodes. I would look into the examples in the NI Example Finder under Toolkits and Modules » FPGA » CompactRIO » Fundamentals » Data Transfer and Storage » Within the FPGA. This directory hosts some really good examples for interloop communication in FPGA code.

[Harjot]

Hi 

In this case ,is it possible to assign a  local variable to  the input data , and then use that variable  in multiple loops.

Regards

Harjot

[0utlaw]

Hello Harjot,

Yes, you can use a local variable in this fashion, however this is a fairly "expensive" method if you don't intend to access these values from the host due to the added array indicator in the FPGA front panel.  You'll also need to be sure that your acquisition loop isn't running faster than your processing loop and/or introduce logic to ensure that you're not overwriting values before they are processed. As Daniel mentioned, I would take a look at VI-scoped FIFOs:

VI-Defined FIFO Configuration Node

http://zone.ni.com/reference/en-XX/help/371599J-01/lvfpga/fpga_vi_scoped_fifo/