Minimum sampling time

[Harjot]

Hello everyone. 

I tried to simplyfy the code by removing the the first loop (DMA FIFO) and by keeping only the control loop so that I have only one loop accessing the Analogue input node (as per attached code).But still with the this simplification , it takes 240 ticks =6us for one loop cycle. The main problem here is the current overshoot .I was trying to  reduce the current overshoot by improving  the sampling time, but I could not get reduction in current overshoot with reduced sampling time. I am applying hysteresis current control with reference current of 60A and a hysteresis band of +-1 A. Ideally the control loop should take the action as soon as it sees a current value higher than 61A. But as per the attached result file, it takes 4-5 samples beyond 61 A , to take the decision. In the meantime the current rises to

67.5A. So it seems to me that the hysteresis function (applied by using Relay VI ) is not performing its task effetively .. If anyone has a opinion on this problem kindly share. 

[[dk]]

The reason you're still seeing a slower acquisition rate is because even though you are only one FPGA I/O node accessing the module, you are implementing additional logic in loop. So the I/O node is going to have to wait for the rest of the code in the loop to finish before it can read again.

I would suggest using the original setup for the user controlled IO sampling and have a second parallel loop that only does the data processing. We can pass the data from the user controlled IO sampling loop to the processing loop using the methods we suggest in previous posts.

[Harjot]

Hi Daniel

Thanks for your reply. Actually for my application , I am Ok with a sampling rate of 6us which I am currently achieved with your suggetsions.The entire code in the control loop is executed in 240 ticks =6us.

My main problem is with the implementation of hystersis current control logic.

For the attached example I am setting a reference current of 150A with a hystersis band of +- 1A that gives lower hystersis limit of149A and upper hysteresis limit of 151A . I am using relay VI to perform hysteresis action. Now as soon as the current value from Input node drops below 149 , My relay VI gives an digital output signal (1) to Output node Mod1/DO1 to turn on the IGBT and current starts increasing. But problem comes when it comes to upper band i.e. 151A . As soon as the current goes higher than 151A , the relay VI shall send digital output (0) to the Mod1/DO1 to turn off the IGBT. But it can be seen from the attched current waveform that  the 0 signal is not sent  to the output node and the switch remains on for 2-3 more loop iterations .The data points on this current waveform indiactes the sampling instances and is captured by using FIFO and is plotted in MATLAB for postprocessing.

Regards

Harjot

[[dk]]

I am curious as to how we are actually getting the current data points. Are we reading the DO line from the 9474 with another device? I wonder if we plot the analog inputs from the 9222 and the desired outputs to the 9474 on the RT controller with DMA FIFOs. This way we can verify what the outputs actually are and when we are outputting low and high to the 9474.

[Harjot]

Hi Daniel 

I tried the logic hysteresis logic by replacing relay VI with S-R flip flop made up off NOR gates. This change didn't improve the result. Then I tried to see the actual gating signal that is passed by control logic to the digital o/p "Mod1/ DO1" by defining a local variable named " logic" and also read the status of "Mod1/ DO1" by using DMA FIFO. All FIFO data was saved in datafile and was plotted in MATLAB for analysis.    With a upper bound of 61A and lower bound  of 59A for hysteresis, as soon as the current from "Mod2/ AI0" goes beyond 61A there should be a low signal passed to Mod2/ DO1 but it takes 3-4 more sampling instances to change the gating signal from 1 to 0. This loop is executing at 6us rate .This results in a switch ON time of 24us and current in this time goes to 67 -68A . Interestingly the logic is respectimg the lower bound very accurately and as soon as current from Mod2/ AI0 falls below 59A , the control logic passes a high signal to :"Mod1/ DO1"