My high speed serial pxie-7902R can't finish generating intermediate files

[ShibukiZero]

I wrote a very simple test program with labview fpga on target 7902R, but it can't generate intermediate files with error code 1. What should I do to fix it?

The error information is like this:

An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with the following information:
Set Permissions in 659XR_GenerateVHDL.vi:3340001->niFpgaTopLevelGenCallTargetSpecificVI.vi->niFpgaHandleConstraintsAndMiscFPGAFiles.vi->niLvFpgaTopModGen.vi->niLvFpgaTopModGen.vi.ProxyCaller
<APPEND>
C:\Program Files\NI\LVAddons\nihss\1\Targets\NI\FPGA\RIO\659XR\PXIe-7902R\FpgaFiles\Templates\PkgChevellePoscROM.vhd

[Intaris]

Your code reduces to a no-op.

Try feeding a feedback node into the negate instead of a constant. Taht way, it will simply toggle the value at the clock rate.

Currently, your entire loop can be removed by Xilinx because it generates a constant output. As such, Xilinx ends up having essentially nothing to compile.

[ShibukiZero]

Actually I tried mmwave reference project and it doesn't work either.

[Intaris]

Are these cloud compiles or local compiles?

Whichever it is, try the other...

Just to rule out one variable.

Or does this error occur before Xilinx even gets involved?