NI5640R FPGA non-diagram component compilation timing error

[thu^^]

I've tried to rebuild the NI5640R example "ni5640R Template" without adding or changing anything.

Got timing error (see below), saying that requirement missed by 0.16ns, because of some non-diagram components: /sDac0Reset, /aDac0Reset_or00001, /aDac0Reset. Xilinx options were set to "use recommended settings".

I've tried this several times, always getting almost the same result. Another example: requirements missed by 0.40ns, because of /sDacSimultReset, /aDac0Reset_or00001, /aDac0Reset. This is still with recommended settings.

Then I tried to compile with design strategy "Timing Performance". 5 out of 6 times compilation failed with timing violation 0.30-0.50ns.

Then I tried to compile with design strategy "Balanced". This time it failed only 2 times out of 6 with timing violation 0.02-0.04ns.

I guess using the "Balanced" strategy works more or less, but maybe there is some better way to address this? I don't even need DAC in my project, so maybe there is a way to exclude it?

[Thoric]

The timing of a particular series of functions in a compile FPGA code is based on the critical combinatorial path (basically the longest path of functions and propagation delays for each given code segment). This result can vary between compilations as the Xilinx compiler works to optimise the placement of each function on the FPGA resource. In this case it looks like it's not working out so well.

Is it possible you changed the FPGA code, or the FPGA target hardware, or added new code to the example? By adding your own code the existing code the Xilinx code has much more optimisation to consider and could ultimately fail to meet the timing criteria.

It's also possible the example worked fine for one particular Xilinx compiler release, but (perhaps ironically) is not able to meet the criteria anymore. I've seen this in my own work.

[thu^^]

I first got this error when trying to compile my own project. Recompiled it several times with the same result. Then I tried to exclude parts of my code to see what is causing this behavior, until I had nothing more than the default configuration loop. Then I thought of trying to recompile "ni5640R Template" to see if at least that works, and still no luck.

What I wrote earlier are results I've got trying to compile "ni5640R Template" without any modifications to the code.

Weirdest part is that I've tried several different projects on NI5640R FPGA earlier and not even once got this error. And then at some point it just started to fail every time. I thought that this might be some kind of software problem, so I uninstalled LV2010 I was using before, and installed LV2013 (extended trial), hoping that maybe this would fix everything, but the problem persists.

Now when I think about it, I should probably try to recompile it on another PC, just to make sure.

[HollyBerry]

Where are you finding the NI5640R Template? I am using LabVIEW 2013 and the NI-5640R Driver Version 1.7. I'm not seeing a project template by that name and the only shipping examples in the example finder for the NI-5640R are:

[thu^^]

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@Holly-S wrote:

Where are you finding the NI5640R Template?

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Examples in your picture are for NI5640R with API. I mentioned, that I have problems compiling the FPGA code. The template for NI5640R FPGA project is available at:

\NI\LabVIEW 2013\examples\instr\ni5640R\FPGA\PCI-5640R\ni5640R Template

[thu^^]

I finally managed to try it out on a different PC. Installed LabVIEW2013, FPGA module, NI5640R v1.7 drivers, updated everything and tried to recompile the Template. As in situation before, the so called "recommended settings" failed most of the time. "Area" and "Timing" strategies also fail all the time. "Balanced" strategy actually does compile the code, and seems to be the only working setting. At least now I know it isn't the system's fault - probably something in Xilinx tools, NI5640R itself, or the way LabVIEW communicates with Xilinx compiler.

Can someone please try it out and confirm this? Maybe it is written somewhere and I have missed it?

[david1147]

hey thu^^,

I tried this with LabVIEW2013, FPGA module, NI5640R v1.7 drivers, and successfully compiled the example template. I'm attatching my screenshots. Please let me know if there is any difference between my experiment and yours.

[thu^^]

I forgot to mention - when compiling, as you can see - every clock meets the requirements. It even successfully generates the programming file, and after that throws the timing error.

Attaching Xilinx Log

[thu^^]

Successfully recompiled using the "Balanced" strategy. Attaching log.

[thu^^]

I've compared the 2 logs just now. There is a timing error alright.

Though I find it a bit confusing that LabVIEW reports that everything is ok and all constraints have been met and bitfile has been successfully compiled, just before throwing this error.

Maybe there is something wrong with Xilinx tools? But then again, david1147 said that he was able to compile it without errors, and I've got errors on two different PCs.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
* TS_RTSI_Ref_Clk = PERIOD TIMEGRP "RtsiRef | SETUP   |    -0.019ns|     4.519ns|       1|          19
  Clk" 4.5 ns HIGH 50%                      | HOLD    |     0.652ns|            |       0|           0
------------------------------------------------------------------------------------------------------

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 1 errors found.