Overflow error cRio NI9222

[jamie_mac]

Hi All

I'm trying to program a cRio 9068 to record data from two synchronised NI 9222 cards, all channels sampling at 500kS/s.  I've been playing around with Labview FPGA and I've managed to read data from the cards, however I've started getting an overwrite error which I'm having issues solving.

I've based my FPGA code on examples in LabView reading NI9222 cards. I have the host vi reading from two Read FIFOs - one reads the number of remaining elements and then the other reads those elements and sends them off to an array which currently doesn not do anything. It all seems to work OK until I start to set the sample rate to around 500kS/s. I then to begin to get overwrite errors and I haven't been able to figure out how to get round the problem.

What's worrying me is that I might have come across a fundamental limit of the cRio- too many samples per second? I've tried to set the 'Requested Number of Elements' in the FIFO properties dialog to 8192 but that flagged up an error in compiling the FPGA. Anyone have any ideas? I'm fairly new to this so would not be surprised if I've done something relatively stupid.

Code is attached.

Cheers

[MariaMK]

Hi Jamie,

It is possible that you have reached the limit of the device, however I have a few questions which will allow me to determine if this is the case.

1. What is the maximum sampling rate you can reach before you get the overwrite error?

2. If you reduce the number of channels can you sample at 500kS/s? If so, what is the maximum number of channels you can sample at this rate?

3. What is the application? If you give me an overview of what you are trying to do I might be able to offer an alternative solution.

Thanks

[jamie_mac]

Hi Maria

Thanks for your reply. To answer your questions:

1) It seems that things are relatively stable at one sample every 4us. Once set to 1 sample every 2us then the FPGA stops working and I get the overwrite error. One thing I have recently noticed is that I have two possible options for selecting the FPGA (see attached pic). If I select RIO0 in the drop down menu of my host vi things are a bit more stable than if I select rio://169.254.232.241/RIO0. Is there an explanation for this- I assumed these were the same thing?

2) I have tried using four channels and everything seems to work OK. Due to the time it takes to compile the FPGA I haven't tried all channels but with 5 channels at 2us sampling things would still fall over every now and then.

3) I am trying to build an application which records 8 channel raw .wav files at 500kS/s. The cRio will be placed in an autonomous buoy, deployed at sea and used to record the vocalisations of harbour porpoises from an array of 8 hydrophones. The reason I must sample at 500kS/s is that harbour porpoises vocalise at 120-150kHz and so sample rates of at least 300kS/s are needed- higher is much better and 500kS/s is the research standard. I'm hoping to convert the FPGA bitfile to a C API so I can program the cRio in eclipse, however I thought it better to get everything working on LabView first.

[speleato]

Hello Jamie,

---

If I select RIO0 in the drop down menu of my host vi things are a bit more stable than if I select rio://169.254.232.241/RIO0. Is there an explanation for this- I assumed these were the same thing?

---

rio://169.254.232.241/RIO0 and RIO0 both reference the same RIO device, but rio://169.254.232.241/RIO0 implies some extra overhead intended to make the FPGA Host Interface work over the network. For RIO devices that are local, you should always use RIO0.

Can you attach your Host VI? I see two copies of the FPGA VI in your original post but I'm missing the Host VI.

When you say overwrite error, do you mean the Overwrite error from the 9022 Get I/O Read Status method?

Thanks,

Sebastian

[jamie_mac]

Hi Sebastian

Thanks for clearing that up. Explains why the cRio crashes more if there is  extra network overhead.

My bad. I've attched the host vi.

Cheers

Jamie

[MariaMK]

Hi Jamie,

Could you please check the CPU usage of the cRIO when you are trying to sample e.g. 5 channels? You can find instructions on how to do this here. 

Regarding programming the cRIO in Eclipse, I have included some resources below which you may find useful in future:

This white paper explains the LabVIEW FPGA compilation process.

Getting Started with C/C++ Development Tools for NI Linux Real-Time 
FPGA Interface C API Example for NI Linux Real-Time

[jamie_mac]

Hi Maria

Thanks for the info- I'vce been working off those already and they're good well learning resources.

I've run 8 channels of data at 1 sample every 3us and have attached a screenshot of CPU usuage. One of CPU's seems to hit 100%. I will run another test with less channels and post soon.

Cheers

Jamie

[jamie_mac]

I have now run using only 5 channels at 1 sample every 2us and 1 sample every 50us. In both cases the CPU of one core hits 100%, the same as when running 8 channels.

As a thought- could the build array inside my while loop be causing problems?-perhaps I could move that outside the loop. Also, would anyone have an idea whether this code would exucute faster if written in C using the C API generator to make an API which can talk to the FPGA?

[speleato]

Jamie,

In the image you posted the CPU utilization spikes to 100% and then falls back down to lower values? Is that because the failure condition was hit? Or does the code continue to run after the 100% spike?

Sebastian

[jamie_mac]

Hi Sebastian

Yep that's when things fail. The CPU stays at 100% when running. It's possible its not an issue as the CPU seems to hit 100% even when everything is stable. I.e. at lower sample rates.